Add AVX MOV{SS,SD}{rr,rm} instructions
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106588 91177308-0d34-0410-b5e6-96231b3b80d8
diff --git a/lib/Target/X86/X86MCCodeEmitter.cpp b/lib/Target/X86/X86MCCodeEmitter.cpp
index 7692bfd..dbdc2b5 100644
--- a/lib/Target/X86/X86MCCodeEmitter.cpp
+++ b/lib/Target/X86/X86MCCodeEmitter.cpp
@@ -714,15 +714,21 @@
// Keep track of the current byte being emitted.
unsigned CurByte = 0;
- // Is this instruction encoded in AVX form?
- bool IsAVXForm = false;
+ // Is this instruction encoded using the AVX VEX prefix?
+ bool HasVEXPrefix = false;
+
+ // It uses the VEX.VVVV field?
+ bool HasVEX_4V = false;
+
+ if ((TSFlags >> 32) & X86II::VEX)
+ HasVEXPrefix = true;
if ((TSFlags >> 32) & X86II::VEX_4V)
- IsAVXForm = true;
+ HasVEX_4V = true;
// FIXME: We should emit the prefixes in exactly the same order as GAS does,
// in order to provide diffability.
- if (!IsAVXForm)
+ if (!HasVEXPrefix)
EmitOpcodePrefix(TSFlags, CurByte, MI, Desc, OS);
else
EmitVEXOpcodePrefix(TSFlags, CurByte, MI, Desc, OS);
@@ -772,7 +778,7 @@
EmitByte(BaseOpcode, CurByte, OS);
SrcRegNum = CurOp + 1;
- if (IsAVXForm) // Skip 1st src (which is encoded in VEX_VVVV)
+ if (HasVEX_4V) // Skip 1st src (which is encoded in VEX_VVVV)
SrcRegNum++;
EmitRegModRMByte(MI.getOperand(SrcRegNum),
@@ -783,7 +789,7 @@
case X86II::MRMSrcMem: {
int AddrOperands = X86AddrNumOperands;
unsigned FirstMemOp = CurOp+1;
- if (IsAVXForm) {
+ if (HasVEX_4V) {
++AddrOperands;
++FirstMemOp; // Skip the register source (which is encoded in VEX_VVVV).
}