commit c46570dc05851395829bef904bb6ddb1260400d1
author Jakob Stoklund Olesen <stoklund@2pi.dk> Wed Mar 16 22:56:08 2011 +0000
committer Jakob Stoklund Olesen <stoklund@2pi.dk> Wed Mar 16 22:56:08 2011 +0000
tree 179a2496f8f6beed6e7129a59a84a99c04760a6d
parent ebe8173941238cfbabadb1c63bca7fb7dcf2adbe

Clarify debugging output.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127771 91177308-0d34-0410-b5e6-96231b3b80d8

lib/CodeGen/RegAllocGreedy.cpp

diff --git a/lib/CodeGen/RegAllocGreedy.cpp b/lib/CodeGen/RegAllocGreedy.cpp
index 57119aa..940ed81 100644
--- a/lib/CodeGen/RegAllocGreedy.cpp
+++ b/lib/CodeGen/RegAllocGreedy.cpp
@@ -646,7 +646,9 @@
     IndexPair &IP = InterferenceRanges[i];
     DEBUG(dbgs() << "BB#" << BI.MBB->getNumber() << " -> EB#"
                  << Bundles->getBundle(BI.MBB->getNumber(), 1)
-                 << " intf [" << IP.first << ';' << IP.second << ')');
+                 << " [" << BI.Start << ';' << BI.LastSplitPoint << '-'
+                 << BI.Stop << ") intf [" << IP.first << ';' << IP.second
+                 << ')');
 
     // The interference interval should either be invalid or overlap MBB.
     assert((!IP.first.isValid() || IP.first < BI.Stop) && "Bad interference");
@@ -741,7 +743,8 @@
     IndexPair &IP = InterferenceRanges[i];
 
     DEBUG(dbgs() << "EB#" << Bundles->getBundle(BI.MBB->getNumber(), 0)
-                 << " -> BB#" << BI.MBB->getNumber());
+                 << " -> BB#" << BI.MBB->getNumber() << " [" << BI.Start << ';'
+                 << BI.LastSplitPoint << '-' << BI.Stop << ')');
 
     // Check interference entering the block.
     if (!IP.first.isValid()) {
@@ -1266,6 +1269,9 @@
   LiveRangeEdit LRE(VirtReg, NewVRegs, this);
   spiller().spill(LRE);
 
+  if (VerifyEnabled)
+    MF->verify(this, "After spilling");
+
   // The live virtual register requesting allocation was spilled, so tell
   // the caller not to allocate anything during this round.
   return 0;