Clean up sub-register implementation by moving subReg information back to
MachineOperand auxInfo. Previous clunky implementation uses an external map
to track sub-register uses. That works because register allocator uses
a new virtual register for each spilled use. With interval splitting (coming
soon), we may have multiple uses of the same register some of which are
of using different sub-registers from others. It's too fragile to constantly
update the information.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@44104 91177308-0d34-0410-b5e6-96231b3b80d8
diff --git a/lib/Target/X86/X86ATTAsmPrinter.cpp b/lib/Target/X86/X86ATTAsmPrinter.cpp
index cee802d..f46ebb8 100644
--- a/lib/Target/X86/X86ATTAsmPrinter.cpp
+++ b/lib/Target/X86/X86ATTAsmPrinter.cpp
@@ -616,6 +616,15 @@
   case X86::PsMOVZX64rr32:
     O << TAI->getCommentString() << " ZERO-EXTEND " << "\n\t";
     break;
+  case X86::MOV8mr: {
+    const MachineOperand &MO = MI->getOperand(4);
+    switch (MO.getReg()) {
+      default: abort();
+      case X86::AH: case X86::DH: case X86::CH: case X86::BH:
+      case X86::AL: case X86::DL: case X86::CL: case X86::BL:
+        break;
+    }
+  }
   }
 
   // Call the autogenerated instruction printer routines.
diff --git a/lib/Target/X86/X86RegisterInfo.cpp b/lib/Target/X86/X86RegisterInfo.cpp
index 71f8d0e..25b6375 100644
--- a/lib/Target/X86/X86RegisterInfo.cpp
+++ b/lib/Target/X86/X86RegisterInfo.cpp
@@ -773,7 +773,8 @@
 static const MachineInstrBuilder &X86InstrAddOperand(MachineInstrBuilder &MIB,
                                                      MachineOperand &MO) {
   if (MO.isRegister())
-    MIB = MIB.addReg(MO.getReg(), MO.isDef(), MO.isImplicit());
+    MIB = MIB.addReg(MO.getReg(), MO.isDef(), MO.isImplicit(),
+                     false, false, MO.getSubReg());
   else if (MO.isImmediate())
     MIB = MIB.addImm(MO.getImm());
   else if (MO.isFrameIndex())
@@ -1498,8 +1499,7 @@
           unsigned Opc = (Amount < 128) ?
             (Is64Bit ? X86::ADD64ri8 : X86::ADD32ri8) :
             (Is64Bit ? X86::ADD64ri32 : X86::ADD32ri);
-          New = BuildMI(TII.get(Opc),  StackPtr)
-                        .addReg(StackPtr).addImm(Amount);
+          New = BuildMI(TII.get(Opc), StackPtr).addReg(StackPtr).addImm(Amount);
         }
       }