implement CodeGen/PowerPC/div-2.ll:test2-4 by propagating zero bits through
C-X's
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23662 91177308-0d34-0410-b5e6-96231b3b80d8
diff --git a/lib/CodeGen/SelectionDAG/DAGCombiner.cpp b/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
index 86ee932..e037f2e 100644
--- a/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
+++ b/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
@@ -205,6 +205,24 @@
return MaskedValueIsZero(Op.getOperand(0), NewVal, TLI);
}
return false;
+ case ISD::SUB:
+ if (ConstantSDNode *CLHS = dyn_cast<ConstantSDNode>(Op.getOperand(0))) {
+ // We know that the top bits of C-X are clear if X contains less bits
+ // than C (i.e. no wrap-around can happen). For example, 20-X is
+ // positive if we can prove that X is >= 0 and < 16.
+ unsigned Bits = MVT::getSizeInBits(CLHS->getValueType(0));
+ if ((CLHS->getValue() & (1 << (Bits-1))) == 0) { // sign bit clear
+ unsigned NLZ = CountLeadingZeros_64(CLHS->getValue()+1);
+ uint64_t MaskV = (1ULL << (63-NLZ))-1;
+ if (MaskedValueIsZero(Op.getOperand(1), ~MaskV, TLI)) {
+ // High bits are clear this value is known to be >= C.
+ unsigned NLZ2 = CountLeadingZeros_64(CLHS->getValue());
+ if ((Mask & ((1ULL << (64-NLZ2))-1)) == 0)
+ return true;
+ }
+ }
+ }
+ break;
case ISD::CTTZ:
case ISD::CTLZ:
case ISD::CTPOP: