Fix a couple bugs in the const div stuff where we'd generate MULHS/MULHU
for types that aren't legal, and fail a divisor is less than zero
comparison, which would cause us to drop a subtract.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23846 91177308-0d34-0410-b5e6-96231b3b80d8
diff --git a/lib/CodeGen/SelectionDAG/DAGCombiner.cpp b/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
index eb0b88d..cf6106d 100644
--- a/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
+++ b/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
@@ -790,7 +790,8 @@
// detect that too.
if (N1C && !isPowerOf2_64(N1C->getSignExtended()) &&
(N1C->getSignExtended() < -1 || N1C->getSignExtended() > 1) &&
- TLI.isOperationLegal(ISD::MULHS, VT) && TLI.isIntDivExpensive()) {
+ TLI.isOperationLegal(ISD::MULHS, VT) && TLI.isTypeLegal(VT) &&
+ TLI.isIntDivExpensive()) {
return BuildSDIV(N);
}
return SDOperand();
@@ -814,7 +815,7 @@
TLI.getShiftAmountTy()));
// fold (udiv x, c) -> alternate
if (N1C && N1C->getValue() && TLI.isOperationLegal(ISD::MULHU, VT) &&
- TLI.isIntDivExpensive())
+ TLI.isTypeLegal(VT) && TLI.isIntDivExpensive())
return BuildUDIV(N);
return SDOperand();
}
@@ -2555,7 +2556,7 @@
assert((VT == MVT::i32 || VT == MVT::i64) &&
"BuildSDIV only operates on i32 or i64!");
- int64_t d = cast<ConstantSDNode>(N->getOperand(1))->getValue();
+ int64_t d = cast<ConstantSDNode>(N->getOperand(1))->getSignExtended();
ms magics = (VT == MVT::i32) ? magic32(d) : magic64(d);
// Multiply the numerator (operand 0) by the magic value