commit c6af2432c802d241c8fffbe0371c023e6c58844e
author Michael J. Spencer <bigcheesegs@gmail.com> Fri May 24 22:23:49 2013 +0000
committer Michael J. Spencer <bigcheesegs@gmail.com> Fri May 24 22:23:49 2013 +0000
tree 98918e0d95a674aa47cd70cefd9bb5b9daed7b48
parent 54c74823885eade8173965f8bb99f026aacb9657

Replace Count{Leading,Trailing}Zeros_{32,64} with count{Leading,Trailing}Zeros.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182680 91177308-0d34-0410-b5e6-96231b3b80d8

lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp

diff --git a/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp b/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
index 1ce2477..9799568 100644
--- a/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
+++ b/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
@@ -1816,7 +1816,7 @@
     Cmp = DAG.getSetCC(getCurDebugLoc(),
                        TLI.getSetCCResultType(*DAG.getContext(), VT),
                        ShiftOp,
-                       DAG.getConstant(CountTrailingZeros_64(B.Mask), VT),
+                       DAG.getConstant(countTrailingZeros(B.Mask), VT),
                        ISD::SETEQ);
   } else if (PopCount == BB.Range) {
     // There is only one zero bit in the range, test for it directly.