For VFP2 fldm, fstm instructions, the condition code is printed after the address mode and size specifier. e.g. fstmiaseq, not fstmeqias.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37351 91177308-0d34-0410-b5e6-96231b3b80d8
diff --git a/lib/Target/ARM/ARMInstrVFP.td b/lib/Target/ARM/ARMInstrVFP.td
index f183891..c0428e9 100644
--- a/lib/Target/ARM/ARMInstrVFP.td
+++ b/lib/Target/ARM/ARMInstrVFP.td
@@ -108,21 +108,21 @@
let isLoad = 1 in {
def FLDMD : AXDI5<(ops addrmode5:$addr, pred:$p, reglist:$dst1, variable_ops),
- "fldm${p}${addr:submode}d ${addr:base}, $dst1",
+ "fldm${addr:submode}d${p} ${addr:base}, $dst1",
[]>;
def FLDMS : AXSI5<(ops addrmode5:$addr, pred:$p, reglist:$dst1, variable_ops),
- "fldm${p}${addr:submode}s ${addr:base}, $dst1",
+ "fldm${addr:submode}s${p} ${addr:base}, $dst1",
[]>;
} // isLoad
let isStore = 1 in {
def FSTMD : AXDI5<(ops addrmode5:$addr, pred:$p, reglist:$src1, variable_ops),
- "fstm${p}${addr:submode}d ${addr:base}, $src1",
+ "fstm${addr:submode}d${p} ${addr:base}, $src1",
[]>;
def FSTMS : AXSI5<(ops addrmode5:$addr, pred:$p, reglist:$src1, variable_ops),
- "fstm${p}${addr:submode}s ${addr:base}, $src1",
+ "fstm${addr:submode}s${p} ${addr:base}, $src1",
[]>;
} // isStore