commit c73488a38ecb26340604706003e84cff7bd48ddf
author Daniel Sanders <daniel.sanders@imgtec.com> Fri Aug 23 10:10:13 2013 +0000
committer Daniel Sanders <daniel.sanders@imgtec.com> Fri Aug 23 10:10:13 2013 +0000
tree d6ebbf76fdba1fac6ae307dafd8aee4ac5314a47
parent bbe88b7f0daf0027bf094d0e9fe36adc5243ca5d

[mips][msa] Split MSA128 regset into size-specific sets containing the same registers.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189095 91177308-0d34-0410-b5e6-96231b3b80d8

lib/Target/Mips/MipsSEISelLowering.cpp

diff --git a/lib/Target/Mips/MipsSEISelLowering.cpp b/lib/Target/Mips/MipsSEISelLowering.cpp
index fb72251..dfa16c0 100644
--- a/lib/Target/Mips/MipsSEISelLowering.cpp
+++ b/lib/Target/Mips/MipsSEISelLowering.cpp
@@ -78,13 +78,13 @@
     setOperationAction(ISD::MUL, MVT::v2i16, Legal);
 
   if (Subtarget->hasMSA()) {
-    addMSAType(MVT::v16i8);
-    addMSAType(MVT::v8i16);
-    addMSAType(MVT::v4i32);
-    addMSAType(MVT::v2i64);
-    addMSAType(MVT::v8f16);
-    addMSAType(MVT::v4f32);
-    addMSAType(MVT::v2f64);
+    addMSAType(MVT::v16i8, &Mips::MSA128BRegClass);
+    addMSAType(MVT::v8i16, &Mips::MSA128HRegClass);
+    addMSAType(MVT::v4i32, &Mips::MSA128WRegClass);
+    addMSAType(MVT::v2i64, &Mips::MSA128DRegClass);
+    addMSAType(MVT::v8f16, &Mips::MSA128HRegClass);
+    addMSAType(MVT::v4f32, &Mips::MSA128WRegClass);
+    addMSAType(MVT::v2f64, &Mips::MSA128DRegClass);
   }
 
   if (!TM.Options.UseSoftFloat) {
@@ -133,9 +133,9 @@
   return new MipsSETargetLowering(TM);
 }
 
-void
-MipsSETargetLowering::addMSAType(MVT::SimpleValueType Ty) {
-  addRegisterClass(Ty, &Mips::MSA128RegClass);
+void MipsSETargetLowering::
+addMSAType(MVT::SimpleValueType Ty, const TargetRegisterClass *RC) {
+  addRegisterClass(Ty, RC);
 
   // Expand all builtin opcodes.
   for (unsigned Opc = 0; Opc < ISD::BUILTIN_OP_END; ++Opc)