commit c89c744b69cecac576317a98322fd295e36e9886
author Craig Topper <craig.topper@gmail.com> Tue Mar 27 07:21:54 2012 +0000
committer Craig Topper <craig.topper@gmail.com> Tue Mar 27 07:21:54 2012 +0000
tree d5dd4765c25f63a4b93c892ed6cf0c0ed32df83d
parent b4549e1c0ecec1b9ea6b0e5ffe01c84c9842d668

Remove unnecessary llvm:: qualifications

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153500 91177308-0d34-0410-b5e6-96231b3b80d8

lib/Target/MBlaze/MBlazeISelLowering.cpp

diff --git a/lib/Target/MBlaze/MBlazeISelLowering.cpp b/lib/Target/MBlaze/MBlazeISelLowering.cpp
index 9ef6bb6..edfc335 100644
--- a/lib/Target/MBlaze/MBlazeISelLowering.cpp
+++ b/lib/Target/MBlaze/MBlazeISelLowering.cpp
@@ -1046,10 +1046,10 @@
 
   // If this function is using the interrupt_handler calling convention
   // then use "rtid r14, 0" otherwise use "rtsd r15, 8"
-  unsigned Ret = (CallConv == llvm::CallingConv::MBLAZE_INTR) ? MBlazeISD::IRet
-                                                              : MBlazeISD::Ret;
-  unsigned Reg = (CallConv == llvm::CallingConv::MBLAZE_INTR) ? MBlaze::R14
-                                                              : MBlaze::R15;
+  unsigned Ret = (CallConv == CallingConv::MBLAZE_INTR) ? MBlazeISD::IRet
+                                                        : MBlazeISD::Ret;
+  unsigned Reg = (CallConv == CallingConv::MBLAZE_INTR) ? MBlaze::R14
+                                                        : MBlaze::R15;
   SDValue DReg = DAG.getRegister(Reg, MVT::i32);
 
   if (Flag.getNode())