commit c8bd287f3c782ae15d0d36720d874b1054dbd143
author Chris Lattner <sabre@nondot.org> Sun Dec 30 01:01:54 2007 +0000
committer Chris Lattner <sabre@nondot.org> Sun Dec 30 01:01:54 2007 +0000
tree 45af90f26dec0254d0e7b7d8200aed021723f797
parent 9ce2e9d5a07cb3e0176cb32838231243829d67c5

use simplified operand addition methods.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45437 91177308-0d34-0410-b5e6-96231b3b80d8

lib/Target/ARM/ARMInstrInfo.cpp

diff --git a/lib/Target/ARM/ARMInstrInfo.cpp b/lib/Target/ARM/ARMInstrInfo.cpp
index 92df991..40a547e 100644
--- a/lib/Target/ARM/ARMInstrInfo.cpp
+++ b/lib/Target/ARM/ARMInstrInfo.cpp
@@ -469,8 +469,8 @@
   unsigned Opc = MI->getOpcode();
   if (Opc == ARM::B || Opc == ARM::tB) {
     MI->setInstrDescriptor(get(Opc == ARM::B ? ARM::Bcc : ARM::tBcc));
-    MI->addImmOperand(Pred[0].getImmedValue());
-    MI->addRegOperand(Pred[1].getReg(), false);
+    MI->addOperand(MachineOperand::CreateImm(Pred[0].getImm()));
+    MI->addOperand(MachineOperand::CreateReg(Pred[1].getReg(), false));
     return true;
   }
 

lib/Target/ARM/ARMRegisterInfo.cpp

diff --git a/lib/Target/ARM/ARMRegisterInfo.cpp b/lib/Target/ARM/ARMRegisterInfo.cpp
index a933e8c..301a829 100644
--- a/lib/Target/ARM/ARMRegisterInfo.cpp
+++ b/lib/Target/ARM/ARMRegisterInfo.cpp
@@ -126,7 +126,7 @@
       PopMI->setInstrDescriptor(TII.get(ARM::tPOP_RET));
       MBB.erase(MI);
     }
-    PopMI->addRegOperand(Reg, true);
+    PopMI->addOperand(MachineOperand::CreateReg(Reg, true));
   }
   return true;
 }
@@ -1100,9 +1100,10 @@
       MI.setInstrDescriptor(TII.get(ARM::tLDR));
       MI.getOperand(i).ChangeToRegister(TmpReg, false, false, true);
       if (UseRR)
-        MI.addRegOperand(FrameReg, false);  // Use [reg, reg] addrmode.
-      else
-        MI.addRegOperand(0, false); // tLDR has an extra register operand.
+        // Use [reg, reg] addrmode.
+        MI.addOperand(MachineOperand::CreateReg(FrameReg, false));
+      else  // tLDR has an extra register operand.
+        MI.addOperand(MachineOperand::CreateReg(0, false));
     } else if (TII.isStore(Opcode)) {
       // FIXME! This is horrific!!! We need register scavenging.
       // Our temporary workaround has marked r3 unavailable. Of course, r3 is
@@ -1134,10 +1135,10 @@
         emitThumbRegPlusImmediate(MBB, II, TmpReg, FrameReg, Offset, TII);
       MI.setInstrDescriptor(TII.get(ARM::tSTR));
       MI.getOperand(i).ChangeToRegister(TmpReg, false, false, true);
-      if (UseRR)
-        MI.addRegOperand(FrameReg, false);  // Use [reg, reg] addrmode.
-      else
-        MI.addRegOperand(0, false); // tSTR has an extra register operand.
+      if (UseRR)  // Use [reg, reg] addrmode.
+        MI.addOperand(MachineOperand::CreateReg(FrameReg, false));
+      else // tSTR has an extra register operand.
+        MI.addOperand(MachineOperand::CreateReg(0, false));
 
       MachineBasicBlock::iterator NII = next(II);
       if (ValReg == ARM::R3)