commit c8eb880a7fb0958a3a048a82c8558beec11f1209
author Craig Topper <craig.topper@gmail.com> Sun Nov 06 23:04:08 2011 +0000
committer Craig Topper <craig.topper@gmail.com> Sun Nov 06 23:04:08 2011 +0000
tree b78bcb93cbee0801c40e6176ccc83d25b62dd637
parent 590853667345d6fb191764b9d0bd2ff13589e3a3

More AVX2 instructions and their intrinsics.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143895 91177308-0d34-0410-b5e6-96231b3b80d8

utils/TableGen/X86DisassemblerTables.cpp

diff --git a/utils/TableGen/X86DisassemblerTables.cpp b/utils/TableGen/X86DisassemblerTables.cpp
index e8c9a48..61e9452 100644
--- a/utils/TableGen/X86DisassemblerTables.cpp
+++ b/utils/TableGen/X86DisassemblerTables.cpp
@@ -95,7 +95,10 @@
   case IC_VEX_L:
   case IC_VEX_L_XS:
   case IC_VEX_L_XD:
+    return false;
   case IC_VEX_L_OPSIZE:
+    return inheritsFrom(child, IC_VEX_L_W_OPSIZE);
+  case IC_VEX_L_W_OPSIZE:
     return false;
   default:
     llvm_unreachable("Unknown instruction class");
@@ -494,7 +497,9 @@
   for (index = 0; index < 256; ++index) {
     o.indent(i * 2);
 
-    if ((index & ATTR_VEXL) && (index & ATTR_OPSIZE))
+    if ((index & ATTR_VEXL) && (index & ATTR_REXW) && (index & ATTR_OPSIZE))
+      o << "IC_VEX_L_W_OPSIZE";
+    else if ((index & ATTR_VEXL) && (index & ATTR_OPSIZE))
       o << "IC_VEX_L_OPSIZE";
     else if ((index & ATTR_VEXL) && (index & ATTR_XD))
       o << "IC_VEX_L_XD";