More AVX instructions ({ADD,SUB,MUL,DIV}{SS,SD}rm)
Introduce the VEX_X field
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105859 91177308-0d34-0410-b5e6-96231b3b80d8
diff --git a/utils/TableGen/X86RecognizableInstr.cpp b/utils/TableGen/X86RecognizableInstr.cpp
index 5fe2bfe..19b51cb 100644
--- a/utils/TableGen/X86RecognizableInstr.cpp
+++ b/utils/TableGen/X86RecognizableInstr.cpp
@@ -535,7 +535,8 @@
HANDLE_OPERAND(rmRegister)
if (HasVEX_4VPrefix)
- // FIXME: encoding of registers in AVX is in 1's complement form.
+ // FIXME: In AVX, the register below becomes the one encoded
+ // in ModRMVEX and the one above the one in the VEX.VVVV field
HANDLE_OPTIONAL(rmRegister)
else
HANDLE_OPTIONAL(immediate)
@@ -547,6 +548,12 @@
assert(numPhysicalOperands >= 2 && numPhysicalOperands <= 3 &&
"Unexpected number of operands for MRMSrcMemFrm");
HANDLE_OPERAND(roRegister)
+
+ if (HasVEX_4VPrefix)
+ // FIXME: In AVX, the register below becomes the one encoded
+ // in ModRMVEX and the one above the one in the VEX.VVVV field
+ HANDLE_OPTIONAL(rmRegister)
+
HANDLE_OPERAND(memory)
HANDLE_OPTIONAL(immediate)
break;