Factor out the code to add a MachineOperand to a MachineInstrBuilder.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@64891 91177308-0d34-0410-b5e6-96231b3b80d8
diff --git a/lib/Target/ARM/ARMInstrInfo.cpp b/lib/Target/ARM/ARMInstrInfo.cpp
index 9dc0785..3277896 100644
--- a/lib/Target/ARM/ARMInstrInfo.cpp
+++ b/lib/Target/ARM/ARMInstrInfo.cpp
@@ -509,20 +509,6 @@
return true;
}
-static const MachineInstrBuilder &ARMInstrAddOperand(MachineInstrBuilder &MIB,
- MachineOperand &MO) {
- if (MO.isReg())
- MIB = MIB.addReg(MO.getReg(), MO.isDef(), MO.isImplicit());
- else if (MO.isImm())
- MIB = MIB.addImm(MO.getImm());
- else if (MO.isFI())
- MIB = MIB.addFrameIndex(MO.getIndex());
- else
- assert(0 && "Unknown operand for ARMInstrAddOperand!");
-
- return MIB;
-}
-
void ARMInstrInfo::
storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
unsigned SrcReg, bool isKill, int FI,
@@ -567,7 +553,7 @@
MachineInstrBuilder MIB =
BuildMI(MF, DL, get(Opc)).addReg(SrcReg, false, false, isKill);
for (unsigned i = 0, e = Addr.size(); i != e; ++i)
- MIB = ARMInstrAddOperand(MIB, Addr[i]);
+ MIB.addOperand(Addr[i]);
NewMIs.push_back(MIB);
return;
}
@@ -582,7 +568,7 @@
MachineInstrBuilder MIB =
BuildMI(MF, DL, get(Opc)).addReg(SrcReg, false, false, isKill);
for (unsigned i = 0, e = Addr.size(); i != e; ++i)
- MIB = ARMInstrAddOperand(MIB, Addr[i]);
+ MIB.addOperand(Addr[i]);
AddDefaultPred(MIB);
NewMIs.push_back(MIB);
return;
@@ -626,7 +612,7 @@
Opc = Addr[0].isFI() ? ARM::tRestore : ARM::tLDR;
MachineInstrBuilder MIB = BuildMI(MF, DL, get(Opc), DestReg);
for (unsigned i = 0, e = Addr.size(); i != e; ++i)
- MIB = ARMInstrAddOperand(MIB, Addr[i]);
+ MIB.addOperand(Addr[i]);
NewMIs.push_back(MIB);
return;
}
@@ -640,7 +626,7 @@
MachineInstrBuilder MIB = BuildMI(MF, DL, get(Opc), DestReg);
for (unsigned i = 0, e = Addr.size(); i != e; ++i)
- MIB = ARMInstrAddOperand(MIB, Addr[i]);
+ MIB.addOperand(Addr[i]);
AddDefaultPred(MIB);
NewMIs.push_back(MIB);
return;