commit c9298235251b014e86a7368d92b589d093acb64a
author Christopher Lamb <christopher.lamb@gmail.com> Sun Mar 16 03:12:01 2008 +0000
committer Christopher Lamb <christopher.lamb@gmail.com> Sun Mar 16 03:12:01 2008 +0000
tree 11c2e0c245fb52c02a65e3e9469f5f83e94abaee
parent 606c5aa084041eb5ad60710728098eaf9c997315

Make insert_subreg a two-address instruction, vastly simplifying LowerSubregs pass. Add a new TII, subreg_to_reg, which is like insert_subreg except that it takes an immediate implicit value to insert into rather than a register.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48412 91177308-0d34-0410-b5e6-96231b3b80d8

utils/TableGen/CodeEmitterGen.cpp

diff --git a/utils/TableGen/CodeEmitterGen.cpp b/utils/TableGen/CodeEmitterGen.cpp
index bebf1fd..a21a31c 100644
--- a/utils/TableGen/CodeEmitterGen.cpp
+++ b/utils/TableGen/CodeEmitterGen.cpp
@@ -30,7 +30,8 @@
         R->getName() == "DECLARE" ||
         R->getName() == "EXTRACT_SUBREG" ||
         R->getName() == "INSERT_SUBREG" ||
-        R->getName() == "IMPLICIT_DEF") continue;
+        R->getName() == "IMPLICIT_DEF" ||
+        R->getName() == "SUBREG_TO_REG") continue;
     
     BitsInit *BI = R->getValueAsBitsInit("Inst");
 
@@ -105,7 +106,8 @@
         R->getName() == "DECLARE" ||
         R->getName() == "EXTRACT_SUBREG" ||
         R->getName() == "INSERT_SUBREG" ||
-        R->getName() == "IMPLICIT_DEF") {
+        R->getName() == "IMPLICIT_DEF" ||
+        R->getName() == "SUBREG_TO_REG") {
       o << "    0U";
       continue;
     }
@@ -139,7 +141,8 @@
         InstName == "DECLARE"||
         InstName == "EXTRACT_SUBREG" ||
         InstName == "INSERT_SUBREG" ||
-        InstName == "IMPLICIT_DEF") continue;
+        InstName == "IMPLICIT_DEF" ||
+        InstName == "SUBREG_TO_REG") continue;
     
     BitsInit *BI = R->getValueAsBitsInit("Inst");
     const std::vector<RecordVal> &Vals = R->getValues();

utils/TableGen/CodeGenTarget.cpp

diff --git a/utils/TableGen/CodeGenTarget.cpp b/utils/TableGen/CodeGenTarget.cpp
index e41f75a..da34ebf 100644
--- a/utils/TableGen/CodeGenTarget.cpp
+++ b/utils/TableGen/CodeGenTarget.cpp
@@ -309,6 +309,11 @@
     throw "Could not find 'IMPLICIT_DEF' instruction!";
   const CodeGenInstruction *IMPLICIT_DEF = &I->second;
   
+  I = getInstructions().find("SUBREG_TO_REG");
+  if (I == Instructions.end())
+    throw "Could not find 'SUBREG_TO_REG' instruction!";
+  const CodeGenInstruction *SUBREG_TO_REG = &I->second;
+  
   // Print out the rest of the instructions now.
   NumberedInstructions.push_back(PHI);
   NumberedInstructions.push_back(INLINEASM);
@@ -317,6 +322,7 @@
   NumberedInstructions.push_back(EXTRACT_SUBREG);
   NumberedInstructions.push_back(INSERT_SUBREG);
   NumberedInstructions.push_back(IMPLICIT_DEF);
+  NumberedInstructions.push_back(SUBREG_TO_REG);
   for (inst_iterator II = inst_begin(), E = inst_end(); II != E; ++II)
     if (&II->second != PHI &&
         &II->second != INLINEASM &&
@@ -324,7 +330,8 @@
         &II->second != DECLARE &&
         &II->second != EXTRACT_SUBREG &&
         &II->second != INSERT_SUBREG &&
-        &II->second != IMPLICIT_DEF)
+        &II->second != IMPLICIT_DEF &&
+        &II->second != SUBREG_TO_REG)
       NumberedInstructions.push_back(&II->second);
 }
 

utils/TableGen/InstrInfoEmitter.cpp

diff --git a/utils/TableGen/InstrInfoEmitter.cpp b/utils/TableGen/InstrInfoEmitter.cpp
index d765152..cc03c6a 100644
--- a/utils/TableGen/InstrInfoEmitter.cpp
+++ b/utils/TableGen/InstrInfoEmitter.cpp
@@ -411,7 +411,8 @@
         R->getName() != "DECLARE" &&
         R->getName() != "EXTRACT_SUBREG" &&
         R->getName() != "INSERT_SUBREG" &&
-        R->getName() != "IMPLICIT_DEF")
+        R->getName() != "IMPLICIT_DEF" &&
+        R->getName() != "SUBREG_TO_REG")
       throw R->getName() + " doesn't have a field named '" + 
             Val->getValue() + "'!";
     return;