commit c9298235251b014e86a7368d92b589d093acb64a
author Christopher Lamb <christopher.lamb@gmail.com> Sun Mar 16 03:12:01 2008 +0000
committer Christopher Lamb <christopher.lamb@gmail.com> Sun Mar 16 03:12:01 2008 +0000
tree 11c2e0c245fb52c02a65e3e9469f5f83e94abaee
parent 606c5aa084041eb5ad60710728098eaf9c997315

Make insert_subreg a two-address instruction, vastly simplifying LowerSubregs pass. Add a new TII, subreg_to_reg, which is like insert_subreg except that it takes an immediate implicit value to insert into rather than a register.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48412 91177308-0d34-0410-b5e6-96231b3b80d8

utils/TableGen/CodeEmitterGen.cpp

diff --git a/utils/TableGen/CodeEmitterGen.cpp b/utils/TableGen/CodeEmitterGen.cpp
index bebf1fd..a21a31c 100644
--- a/utils/TableGen/CodeEmitterGen.cpp
+++ b/utils/TableGen/CodeEmitterGen.cpp
@@ -30,7 +30,8 @@
         R->getName() == "DECLARE" ||
         R->getName() == "EXTRACT_SUBREG" ||
         R->getName() == "INSERT_SUBREG" ||
-        R->getName() == "IMPLICIT_DEF") continue;
+        R->getName() == "IMPLICIT_DEF" ||
+        R->getName() == "SUBREG_TO_REG") continue;
     
     BitsInit *BI = R->getValueAsBitsInit("Inst");
 
@@ -105,7 +106,8 @@
         R->getName() == "DECLARE" ||
         R->getName() == "EXTRACT_SUBREG" ||
         R->getName() == "INSERT_SUBREG" ||
-        R->getName() == "IMPLICIT_DEF") {
+        R->getName() == "IMPLICIT_DEF" ||
+        R->getName() == "SUBREG_TO_REG") {
       o << "    0U";
       continue;
     }
@@ -139,7 +141,8 @@
         InstName == "DECLARE"||
         InstName == "EXTRACT_SUBREG" ||
         InstName == "INSERT_SUBREG" ||
-        InstName == "IMPLICIT_DEF") continue;
+        InstName == "IMPLICIT_DEF" ||
+        InstName == "SUBREG_TO_REG") continue;
     
     BitsInit *BI = R->getValueAsBitsInit("Inst");
     const std::vector<RecordVal> &Vals = R->getValues();