initial step at adding a dag-to-dag isel for X86 backend. Patch contributed
by Evan Cheng!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24371 91177308-0d34-0410-b5e6-96231b3b80d8
diff --git a/lib/Target/X86/X86TargetMachine.cpp b/lib/Target/X86/X86TargetMachine.cpp
index 4862a23..1d87152 100644
--- a/lib/Target/X86/X86TargetMachine.cpp
+++ b/lib/Target/X86/X86TargetMachine.cpp
@@ -47,6 +47,9 @@
cl::location(X86ScalarSSE),
cl::init(false));
+ cl::opt<bool> EnableX86DAGDAG("enable-x86-dag-isel", cl::Hidden,
+ cl::desc("Enable DAG-to-DAG isel for X86"));
+
// FIXME: This should eventually be handled with target triples and
// subtarget support!
cl::opt<X86VectorEnum, true>
@@ -124,7 +127,10 @@
PM.add(createUnreachableBlockEliminationPass());
// Install an instruction selector.
- PM.add(createX86ISelPattern(*this));
+ if (EnableX86DAGDAG)
+ PM.add(createX86ISelDag(*this));
+ else
+ PM.add(createX86ISelPattern(*this));
// Run optional SSA-based machine code optimizations next...
if (!NoSSAPeephole)
@@ -192,7 +198,10 @@
PM.add(createUnreachableBlockEliminationPass());
// Install an instruction selector.
- PM.add(createX86ISelPattern(TM));
+ if (EnableX86DAGDAG)
+ PM.add(createX86ISelDag(TM));
+ else
+ PM.add(createX86ISelPattern(TM));
// Run optional SSA-based machine code optimizations next...
if (!NoSSAPeephole)