Change latency of SETX to improve schedule -- just a hack.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@1304 91177308-0d34-0410-b5e6-96231b3b80d8
diff --git a/lib/Target/SparcV9/SparcV9Instr.def b/lib/Target/SparcV9/SparcV9Instr.def
index 89322ff..02d5c8e 100644
--- a/lib/Target/SparcV9/SparcV9Instr.def
+++ b/lib/Target/SparcV9/SparcV9Instr.def
@@ -46,7 +46,7 @@
// Use a latency > 1 since this may generate as many as 3 instructions.
I(SETSW, "setsw", 2, 1, 0, true , 0, 2, SPARC_IEUN, M_INT_FLAG | M_ARITH_FLAG | M_PSEUDO_FLAG )
I(SETUW, "setuw", 2, 1, 0, false, 0, 2, SPARC_IEUN, M_INT_FLAG | M_LOGICAL_FLAG | M_ARITH_FLAG | M_PSEUDO_FLAG )
-I(SETX, "setx", 3, 2, 0, true, 0, 5, SPARC_IEUN, M_INT_FLAG | M_LOGICAL_FLAG | M_ARITH_FLAG | M_PSEUDO_FLAG )
+I(SETX, "setx", 3, 2, 0, true, 0, 2, SPARC_IEUN, M_INT_FLAG | M_LOGICAL_FLAG | M_ARITH_FLAG | M_PSEUDO_FLAG )
// Set high-order bits of register and clear low-order bits
I(SETHI, "sethi", 2, 1, B22, false, 0, 1, SPARC_IEUN, M_INT_FLAG | M_LOGICAL_FLAG | M_ARITH_FLAG)