commit c9df025e33ac435adb3b3318d237c36ca7cec659
author Jakob Stoklund Olesen <stoklund@2pi.dk> Mon Jan 10 02:58:51 2011 +0000
committer Jakob Stoklund Olesen <stoklund@2pi.dk> Mon Jan 10 02:58:51 2011 +0000
tree 80a9dfcbb33fcfa3fbfdff2b2f9e6ba80ed170fc
parent fdc8f2d2604877d80f64e309d4b03ea67addf037

Simplify a bunch of isVirtualRegister() and isPhysicalRegister() logic.

These functions not longer assert when passed 0, but simply return false instead.

No functional change intended.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123155 91177308-0d34-0410-b5e6-96231b3b80d8

lib/CodeGen/MachineLICM.cpp

diff --git a/lib/CodeGen/MachineLICM.cpp b/lib/CodeGen/MachineLICM.cpp
index e3b21c4..7766e11 100644
--- a/lib/CodeGen/MachineLICM.cpp
+++ b/lib/CodeGen/MachineLICM.cpp
@@ -622,7 +622,7 @@
       if (!MO.isReg() || MO.isImplicit())
         continue;
       unsigned Reg = MO.getReg();
-      if (!Reg || TargetRegisterInfo::isPhysicalRegister(Reg))
+      if (!TargetRegisterInfo::isVirtualRegister(Reg))
         continue;
 
       bool isNew = RegSeen.insert(Reg);
@@ -655,7 +655,7 @@
     if (!MO.isReg() || MO.isImplicit())
       continue;
     unsigned Reg = MO.getReg();
-    if (!Reg || TargetRegisterInfo::isPhysicalRegister(Reg))
+    if (!TargetRegisterInfo::isVirtualRegister(Reg))
       continue;
 
     bool isNew = RegSeen.insert(Reg);
@@ -889,7 +889,7 @@
     if (!MO.isReg() || MO.isImplicit())
       continue;
     unsigned Reg = MO.getReg();
-    if (!Reg || TargetRegisterInfo::isPhysicalRegister(Reg))
+    if (!TargetRegisterInfo::isVirtualRegister(Reg))
       continue;
 
     const TargetRegisterClass *RC = MRI->getRegClass(Reg);
@@ -952,7 +952,7 @@
       if (!MO.isReg() || MO.isImplicit())
         continue;
       unsigned Reg = MO.getReg();
-      if (!Reg || TargetRegisterInfo::isPhysicalRegister(Reg))
+      if (!TargetRegisterInfo::isVirtualRegister(Reg))
         continue;
       if (MO.isDef()) {
         if (HasHighOperandLatency(MI, i, Reg)) {