Change target-specific classes to use more precise static types.
This eliminates the need for several awkward casts, including
the last dynamic_cast under lib/Target.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@51091 91177308-0d34-0410-b5e6-96231b3b80d8
diff --git a/lib/Target/Alpha/Alpha.h b/lib/Target/Alpha/Alpha.h
index 40725af..77b404f 100644
--- a/lib/Target/Alpha/Alpha.h
+++ b/lib/Target/Alpha/Alpha.h
@@ -25,7 +25,7 @@
class MachineCodeEmitter;
FunctionPass *createAlphaSimpleInstructionSelector(TargetMachine &TM);
- FunctionPass *createAlphaISelDag(TargetMachine &TM);
+ FunctionPass *createAlphaISelDag(AlphaTargetMachine &TM);
FunctionPass *createAlphaCodePrinterPass(std::ostream &OS,
TargetMachine &TM);
FunctionPass *createAlphaPatternInstructionSelector(TargetMachine &TM);
diff --git a/lib/Target/Alpha/AlphaISelDAGToDAG.cpp b/lib/Target/Alpha/AlphaISelDAGToDAG.cpp
index b0ca39b..303c5aa 100644
--- a/lib/Target/Alpha/AlphaISelDAGToDAG.cpp
+++ b/lib/Target/Alpha/AlphaISelDAGToDAG.cpp
@@ -146,9 +146,9 @@
}
public:
- AlphaDAGToDAGISel(TargetMachine &TM)
+ explicit AlphaDAGToDAGISel(AlphaTargetMachine &TM)
: SelectionDAGISel(AlphaLowering),
- AlphaLowering(*(AlphaTargetLowering*)(TM.getTargetLowering()))
+ AlphaLowering(*TM.getTargetLowering())
{}
/// getI64Imm - Return a target constant with the specified value, of type
@@ -559,6 +559,6 @@
/// createAlphaISelDag - This pass converts a legalized DAG into a
/// Alpha-specific DAG, ready for instruction scheduling.
///
-FunctionPass *llvm::createAlphaISelDag(TargetMachine &TM) {
+FunctionPass *llvm::createAlphaISelDag(AlphaTargetMachine &TM) {
return new AlphaDAGToDAGISel(TM);
}
diff --git a/lib/Target/Alpha/AlphaInstrInfo.h b/lib/Target/Alpha/AlphaInstrInfo.h
index 0b51f2d..063eb0c 100644
--- a/lib/Target/Alpha/AlphaInstrInfo.h
+++ b/lib/Target/Alpha/AlphaInstrInfo.h
@@ -28,7 +28,7 @@
/// such, whenever a client has an instance of instruction info, it should
/// always be able to get register info as well (through this method).
///
- virtual const TargetRegisterInfo &getRegisterInfo() const { return RI; }
+ virtual const AlphaRegisterInfo &getRegisterInfo() const { return RI; }
/// Return true if the instruction is a register to register move and
/// leave the source and dest operands in the passed parameters.
diff --git a/lib/Target/Alpha/AlphaTargetMachine.h b/lib/Target/Alpha/AlphaTargetMachine.h
index d365b7d..eab34c2 100644
--- a/lib/Target/Alpha/AlphaTargetMachine.h
+++ b/lib/Target/Alpha/AlphaTargetMachine.h
@@ -42,15 +42,15 @@
virtual const AlphaInstrInfo *getInstrInfo() const { return &InstrInfo; }
virtual const TargetFrameInfo *getFrameInfo() const { return &FrameInfo; }
- virtual const TargetSubtarget *getSubtargetImpl() const{ return &Subtarget; }
- virtual const TargetRegisterInfo *getRegisterInfo() const {
+ virtual const AlphaSubtarget *getSubtargetImpl() const{ return &Subtarget; }
+ virtual const AlphaRegisterInfo *getRegisterInfo() const {
return &InstrInfo.getRegisterInfo();
}
- virtual TargetLowering* getTargetLowering() const {
+ virtual AlphaTargetLowering* getTargetLowering() const {
return const_cast<AlphaTargetLowering*>(&TLInfo);
}
virtual const TargetData *getTargetData() const { return &DataLayout; }
- virtual TargetJITInfo* getJITInfo() {
+ virtual AlphaJITInfo* getJITInfo() {
return &JITInfo;
}