Add preliminary v2f32 support for SPU. Like with v2i32, we just
duplicate the instructions and operate on half vectors.
Also reorder code in SPUInstrInfo.td for better coherency.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110037 91177308-0d34-0410-b5e6-96231b3b80d8
diff --git a/lib/Target/CellSPU/SPUISelLowering.cpp b/lib/Target/CellSPU/SPUISelLowering.cpp
index bcde579..83726f2 100644
--- a/lib/Target/CellSPU/SPUISelLowering.cpp
+++ b/lib/Target/CellSPU/SPUISelLowering.cpp
@@ -428,6 +428,7 @@
// "Odd size" vector classes that we're willing to support:
addRegisterClass(MVT::v2i32, SPU::VECREGRegisterClass);
+ addRegisterClass(MVT::v2f32, SPU::VECREGRegisterClass);
for (unsigned i = (unsigned)MVT::FIRST_VECTOR_VALUETYPE;
i <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++i) {
@@ -1068,6 +1069,7 @@
case MVT::v8i16:
case MVT::v16i8:
case MVT::v2i32:
+ case MVT::v2f32:
ArgRegClass = &SPU::VECREGRegClass;
break;
}