1. Introduce a new TargetOperandInfo::getRegClass() helper method
and convert code to using it, instead of having lots of things
poke the isLookupPtrRegClass() method directly.
2. Make PointerLikeRegClass contain a 'kind' int, and store it in
the existing regclass field of TargetOperandInfo when the
isLookupPtrRegClass() predicate is set. Make getRegClass pass
this into TargetRegisterInfo::getPointerRegClass(), allowing
targets to have multiple ptr_rc things.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77504 91177308-0d34-0410-b5e6-96231b3b80d8
diff --git a/lib/Target/TargetInstrInfo.cpp b/lib/Target/TargetInstrInfo.cpp
index ceaea0c..afbadbf 100644
--- a/lib/Target/TargetInstrInfo.cpp
+++ b/lib/Target/TargetInstrInfo.cpp
@@ -37,14 +37,23 @@
return !isPredicated(MI);
}
+/// getRegClass - Get the register class for the operand, handling resolution
+/// of "symbolic" pointer register classes etc. If this is not a register
+/// operand, this returns null.
+const TargetRegisterClass *
+TargetOperandInfo::getRegClass(const TargetRegisterInfo *TRI) const {
+ if (isLookupPtrRegClass())
+ return TRI->getPointerRegClass(RegClass);
+ return TRI->getRegClass(RegClass);
+}
+
/// getInstrOperandRegClass - Return register class of the operand of an
/// instruction of the specified TargetInstrDesc.
const TargetRegisterClass*
llvm::getInstrOperandRegClass(const TargetRegisterInfo *TRI,
- const TargetInstrDesc &II, unsigned Op) {
+ const TargetInstrDesc &II, unsigned Op) {
+ // FIXME: Should be an assert!
if (Op >= II.getNumOperands())
return NULL;
- if (II.OpInfo[Op].isLookupPtrRegClass())
- return TRI->getPointerRegClass();
- return TRI->getRegClass(II.OpInfo[Op].RegClass);
+ return II.OpInfo[Op].getRegClass(TRI);
}
diff --git a/lib/Target/X86/X86InstrInfo.cpp b/lib/Target/X86/X86InstrInfo.cpp
index e3da39a..4b29305 100644
--- a/lib/Target/X86/X86InstrInfo.cpp
+++ b/lib/Target/X86/X86InstrInfo.cpp
@@ -2381,8 +2381,7 @@
const TargetInstrDesc &TID = get(Opc);
const TargetOperandInfo &TOI = TID.OpInfo[Index];
- const TargetRegisterClass *RC = TOI.isLookupPtrRegClass()
- ? RI.getPointerRegClass() : RI.getRegClass(TOI.RegClass);
+ const TargetRegisterClass *RC = TOI.getRegClass(&RI);
SmallVector<MachineOperand, X86AddrNumOperands> AddrOps;
SmallVector<MachineOperand,2> BeforeOps;
SmallVector<MachineOperand,2> AfterOps;
@@ -2460,9 +2459,7 @@
// Emit the store instruction.
if (UnfoldStore) {
- const TargetOperandInfo &DstTOI = TID.OpInfo[0];
- const TargetRegisterClass *DstRC = DstTOI.isLookupPtrRegClass()
- ? RI.getPointerRegClass() : RI.getRegClass(DstTOI.RegClass);
+ const TargetRegisterClass *DstRC = TID.OpInfo[0].getRegClass(&RI);
storeRegToAddr(MF, Reg, true, AddrOps, DstRC, NewMIs);
}
@@ -2484,9 +2481,7 @@
bool FoldedLoad = I->second.second & (1 << 4);
bool FoldedStore = I->second.second & (1 << 5);
const TargetInstrDesc &TID = get(Opc);
- const TargetOperandInfo &TOI = TID.OpInfo[Index];
- const TargetRegisterClass *RC = TOI.isLookupPtrRegClass()
- ? RI.getPointerRegClass() : RI.getRegClass(TOI.RegClass);
+ const TargetRegisterClass *RC = TID.OpInfo[Index].getRegClass(&RI);
unsigned NumDefs = TID.NumDefs;
std::vector<SDValue> AddrOps;
std::vector<SDValue> BeforeOps;
@@ -2521,9 +2516,7 @@
std::vector<MVT> VTs;
const TargetRegisterClass *DstRC = 0;
if (TID.getNumDefs() > 0) {
- const TargetOperandInfo &DstTOI = TID.OpInfo[0];
- DstRC = DstTOI.isLookupPtrRegClass()
- ? RI.getPointerRegClass() : RI.getRegClass(DstTOI.RegClass);
+ DstRC = TID.OpInfo[0].getRegClass(&RI);
VTs.push_back(*DstRC->vt_begin());
}
for (unsigned i = 0, e = N->getNumValues(); i != e; ++i) {