commit cbd9a19b5d6ff93efa82c467508ede78b8af3bac
author Nadav Rotem <nrotem@apple.com> Thu Oct 18 23:22:48 2012 +0000
committer Nadav Rotem <nrotem@apple.com> Thu Oct 18 23:22:48 2012 +0000
tree 6e0e27c23dc4e189b0e959be3135b60c05b08759
parent ebd3f27c7e2c6c3a1b76786da0d0205a5fdb1ef5

Reapply the TargerTransformInfo changes, minus the changes to LSR and Lowerinvoke.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166248 91177308-0d34-0410-b5e6-96231b3b80d8

lib/Target/ARM/ARMTargetMachine.cpp

diff --git a/lib/Target/ARM/ARMTargetMachine.cpp b/lib/Target/ARM/ARMTargetMachine.cpp
index 6fdf873..c51ae24 100644
--- a/lib/Target/ARM/ARMTargetMachine.cpp
+++ b/lib/Target/ARM/ARMTargetMachine.cpp
@@ -71,7 +71,8 @@
     ELFWriterInfo(*this),
     TLInfo(*this),
     TSInfo(*this),
-    FrameLowering(Subtarget) {
+    FrameLowering(Subtarget),
+    STTI(&TLInfo) {
   if (!Subtarget.hasARMOps())
     report_fatal_error("CPU: '" + Subtarget.getCPUString() + "' does not "
                        "support ARM mode execution!");
@@ -104,7 +105,8 @@
     TSInfo(*this),
     FrameLowering(Subtarget.hasThumb2()
               ? new ARMFrameLowering(Subtarget)
-              : (ARMFrameLowering*)new Thumb1FrameLowering(Subtarget)) {
+              : (ARMFrameLowering*)new Thumb1FrameLowering(Subtarget)),
+    STTI(&TLInfo){
 }
 
 namespace {