Fix FreeBench/fourinarow with the dag isel, by not adding a bogus result
to SHIFT_PARTS nodes
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23151 91177308-0d34-0410-b5e6-96231b3b80d8
diff --git a/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp b/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
index db3b33a..758fd2d 100644
--- a/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
+++ b/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
@@ -2388,10 +2388,7 @@
Ops.push_back(LHSL);
Ops.push_back(LHSH);
Ops.push_back(Amt);
- std::vector<MVT::ValueType> VTs;
- VTs.push_back(LHSL.getValueType());
- VTs.push_back(LHSH.getValueType());
- VTs.push_back(Amt.getValueType());
+ std::vector<MVT::ValueType> VTs(2, LHSL.getValueType());
Lo = DAG.getNode(NodeOp, VTs, Ops);
Hi = Lo.getValue(1);
}