commit cc8cd0cbf12c12916d4b38ef0de5be5501c8270e
author Chris Lattner <sabre@nondot.org> Mon Jan 07 02:48:55 2008 +0000
committer Chris Lattner <sabre@nondot.org> Mon Jan 07 02:48:55 2008 +0000
tree 5f6826d4941017ac8ed24e65dfea73d2bdfb3714
parent ba6da5d5b72618c836ebc3a7613583a16bc8ceac

remove MachineOpCode typedef.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45679 91177308-0d34-0410-b5e6-96231b3b80d8

lib/Target/PowerPC/PPCInstrInfo.cpp

diff --git a/lib/Target/PowerPC/PPCInstrInfo.cpp b/lib/Target/PowerPC/PPCInstrInfo.cpp
index 4d404a5..47e2871 100644
--- a/lib/Target/PowerPC/PPCInstrInfo.cpp
+++ b/lib/Target/PowerPC/PPCInstrInfo.cpp
@@ -37,7 +37,7 @@
 bool PPCInstrInfo::isMoveInstr(const MachineInstr& MI,
                                unsigned& sourceReg,
                                unsigned& destReg) const {
-  MachineOpCode oc = MI.getOpcode();
+  unsigned oc = MI.getOpcode();
   if (oc == PPC::OR || oc == PPC::OR8 || oc == PPC::VOR ||
       oc == PPC::OR4To8 || oc == PPC::OR8To4) {                // or r1, r2, r2
     assert(MI.getNumOperands() >= 3 &&