Do not isel load folding bt instructions for pentium m, core, core2, and AMD processors. These are significantly slower than a load followed by a bt of a register.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@61557 91177308-0d34-0410-b5e6-96231b3b80d8
diff --git a/test/CodeGen/X86/bt.ll b/test/CodeGen/X86/bt.ll
index bc77a58..b63a3f8 100644
--- a/test/CodeGen/X86/bt.ll
+++ b/test/CodeGen/X86/bt.ll
@@ -1,4 +1,6 @@
; RUN: llvm-as < %s | llc | grep btl
+; RUN: llvm-as < %s | llc -mcpu=pentium4 | grep btl | grep esp
+; RUN: llvm-as < %s | llc -mcpu=penryn | grep btl | not grep esp
; PR3253
target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:128:128"
target triple = "i386-apple-darwin8"