diff --git a/lib/CodeGen/SelectionDAG/TargetLowering.cpp b/lib/CodeGen/SelectionDAG/TargetLowering.cpp
index 389f2ea..12185a3 100644
--- a/lib/CodeGen/SelectionDAG/TargetLowering.cpp
+++ b/lib/CodeGen/SelectionDAG/TargetLowering.cpp
@@ -1380,9 +1380,12 @@
                                    BitWidth - InnerVT.getSizeInBits()) &
                DemandedMask) == 0 &&
             isTypeDesirableForOp(ISD::SHL, InnerVT)) {
+          EVT ShTy = getShiftAmountTy();
+          if (!APInt(BitWidth, ShAmt).isIntN(ShTy.getSizeInBits()))
+            ShTy = InnerVT;
           SDValue NarrowShl =
             TLO.DAG.getNode(ISD::SHL, dl, InnerVT, InnerOp,
-                            TLO.DAG.getConstant(ShAmt, InnerVT));
+                            TLO.DAG.getConstant(ShAmt, ShTy));
           return
             TLO.CombineTo(Op,
                           TLO.DAG.getNode(ISD::ANY_EXTEND, dl, Op.getValueType(),
diff --git a/test/CodeGen/X86/shl-anyext.ll b/test/CodeGen/X86/shl-anyext.ll
index 6dc9531..10d489b 100644
--- a/test/CodeGen/X86/shl-anyext.ll
+++ b/test/CodeGen/X86/shl-anyext.ll
@@ -16,3 +16,25 @@
   store i32 %conv820, i32* %p
   ret void
 }
+
+; CHECK: foo:
+
+declare void @bar(i64)
+
+define fastcc void @foo(i32 %t) {
+bb:
+  %tmp = add i32 %t, -1                           ; <i32> [#uses=1]
+  br label %bb1
+
+bb1:                                              ; preds = %bb
+  %tmp2 = zext i32 %tmp to i64                    ; <i64> [#uses=2]
+  %tmp3 = add i64 %tmp2, 1                        ; <i64> [#uses=1]
+  %tmp4 = xor i64 %tmp2, 536870911                ; <i64> [#uses=1]
+  %tmp5 = and i64 %tmp3, %tmp4                    ; <i64> [#uses=1]
+  %tmp6 = shl i64 %tmp5, 3                        ; <i64> [#uses=1]
+  %tmp7 = sub i64 64, %tmp6                       ; <i64> [#uses=1]
+  %tmp8 = and i64 %tmp7, 4294967288               ; <i64> [#uses=1]
+  %tmp9 = lshr i64 -1, %tmp8                      ; <i64> [#uses=1]
+  call void @bar(i64 %tmp9)
+  ret void
+}