commit cdd66b524f62ef6acd6bfa4e586edf8a406c4928
author Nate Begeman <natebegeman@mac.com> Tue Sep 28 21:01:45 2004 +0000
committer Nate Begeman <natebegeman@mac.com> Tue Sep 28 21:01:45 2004 +0000
tree cb828c35e8a197955f69fee8c438f5443414cd44
parent 5b71d3af35f941585acb50de4909cff20f68680d

Add support for the isLoad and isStore flags, needed by the instruction scheduler


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@16554 91177308-0d34-0410-b5e6-96231b3b80d8

utils/TableGen/CodeGenTarget.cpp

diff --git a/utils/TableGen/CodeGenTarget.cpp b/utils/TableGen/CodeGenTarget.cpp
index ba21405..f7225f0 100644
--- a/utils/TableGen/CodeGenTarget.cpp
+++ b/utils/TableGen/CodeGenTarget.cpp
@@ -195,6 +195,8 @@
   isBranch     = R->getValueAsBit("isBranch");
   isBarrier    = R->getValueAsBit("isBarrier");
   isCall       = R->getValueAsBit("isCall");
+  isLoad       = R->getValueAsBit("isLoad");
+  isStore      = R->getValueAsBit("isStore");
   isTwoAddress = R->getValueAsBit("isTwoAddress");
   isTerminator = R->getValueAsBit("isTerminator");
   hasDelaySlot = R->getValueAsBit("hasDelaySlot");