Simplify uses of MVT and EVT. An MVT can be compared directly
with a SimpleValueType, while an EVT supports equality and
inequality comparisons with SimpleValueType.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118169 91177308-0d34-0410-b5e6-96231b3b80d8
diff --git a/lib/Target/ARM/ARMFastISel.cpp b/lib/Target/ARM/ARMFastISel.cpp
index eca3d51..0982ca0 100644
--- a/lib/Target/ARM/ARMFastISel.cpp
+++ b/lib/Target/ARM/ARMFastISel.cpp
@@ -371,7 +371,7 @@
// TODO: Don't worry about 64-bit now, but when this is fixed remove the
// checks from the various callers.
unsigned ARMFastISel::ARMMoveToFPReg(EVT VT, unsigned SrcReg) {
- if (VT.getSimpleVT().SimpleTy == MVT::f64) return 0;
+ if (VT == MVT::f64) return 0;
unsigned MoveReg = createResultReg(TLI.getRegClassFor(VT));
AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
@@ -381,7 +381,7 @@
}
unsigned ARMFastISel::ARMMoveToIntReg(EVT VT, unsigned SrcReg) {
- if (VT.getSimpleVT().SimpleTy == MVT::i64) return 0;
+ if (VT == MVT::i64) return 0;
unsigned MoveReg = createResultReg(TLI.getRegClassFor(VT));
AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
@@ -395,7 +395,7 @@
// the combined constant into an FP reg.
unsigned ARMFastISel::ARMMaterializeFP(const ConstantFP *CFP, EVT VT) {
const APFloat Val = CFP->getValueAPF();
- bool is64bit = VT.getSimpleVT().SimpleTy == MVT::f64;
+ bool is64bit = VT == MVT::f64;
// This checks to see if we can use VFP3 instructions to materialize
// a constant, otherwise we have to go through the constant pool.
@@ -432,7 +432,7 @@
unsigned ARMFastISel::ARMMaterializeInt(const Constant *C, EVT VT) {
// For now 32-bit only.
- if (VT.getSimpleVT().SimpleTy != MVT::i32) return false;
+ if (VT != MVT::i32) return false;
// MachineConstantPool wants an explicit alignment.
unsigned Align = TD.getPrefTypeAlignment(C->getType());
@@ -459,7 +459,7 @@
unsigned ARMFastISel::ARMMaterializeGV(const GlobalValue *GV, EVT VT) {
// For now 32-bit only.
- if (VT.getSimpleVT().SimpleTy != MVT::i32) return 0;
+ if (VT != MVT::i32) return 0;
Reloc::Model RelocM = TM.getRelocationModel();
@@ -1292,8 +1292,7 @@
if (Op2 == 0) return false;
unsigned Opc;
- bool is64bit = VT.getSimpleVT().SimpleTy == MVT::f64 ||
- VT.getSimpleVT().SimpleTy == MVT::i64;
+ bool is64bit = VT == MVT::f64 || VT == MVT::i64;
switch (ISDOpcode) {
default: return false;
case ISD::FADD:
diff --git a/lib/Target/ARM/ARMISelDAGToDAG.cpp b/lib/Target/ARM/ARMISelDAGToDAG.cpp
index 5b28399..ee3ffef 100644
--- a/lib/Target/ARM/ARMISelDAGToDAG.cpp
+++ b/lib/Target/ARM/ARMISelDAGToDAG.cpp
@@ -2240,12 +2240,11 @@
EVT VecVT = N->getValueType(0);
EVT EltVT = VecVT.getVectorElementType();
unsigned NumElts = VecVT.getVectorNumElements();
- if (EltVT.getSimpleVT() == MVT::f64) {
+ if (EltVT == MVT::f64) {
assert(NumElts == 2 && "unexpected type for BUILD_VECTOR");
return PairDRegs(VecVT, N->getOperand(0), N->getOperand(1));
}
- assert(EltVT.getSimpleVT() == MVT::f32 &&
- "unexpected type for BUILD_VECTOR");
+ assert(EltVT == MVT::f32 && "unexpected type for BUILD_VECTOR");
if (NumElts == 2)
return PairSRegs(VecVT, N->getOperand(0), N->getOperand(1));
assert(NumElts == 4 && "unexpected type for BUILD_VECTOR");
diff --git a/lib/Target/ARM/ARMISelLowering.cpp b/lib/Target/ARM/ARMISelLowering.cpp
index 6bd8503..a9a8c88 100644
--- a/lib/Target/ARM/ARMISelLowering.cpp
+++ b/lib/Target/ARM/ARMISelLowering.cpp
@@ -3832,7 +3832,7 @@
} else if ((N0->getOpcode() == ISD::ZERO_EXTEND || ISD::isZEXTLoad(N0)) &&
(N1->getOpcode() == ISD::ZERO_EXTEND || ISD::isZEXTLoad(N1))) {
NewOpc = ARMISD::VMULLu;
- } else if (VT.getSimpleVT().SimpleTy == MVT::v2i64) {
+ } else if (VT == MVT::v2i64) {
// Fall through to expand this. It is not legal.
return SDValue();
} else {