[mips][msa] Added support for matching slli, srai, and srli from normal IR (i.e. not intrinsics)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191285 91177308-0d34-0410-b5e6-96231b3b80d8
diff --git a/lib/Target/Mips/MipsSEISelLowering.cpp b/lib/Target/Mips/MipsSEISelLowering.cpp
index 60960d6..9bd3be2 100644
--- a/lib/Target/Mips/MipsSEISelLowering.cpp
+++ b/lib/Target/Mips/MipsSEISelLowering.cpp
@@ -1187,16 +1187,34 @@
case Intrinsic::mips_sll_w:
case Intrinsic::mips_sll_d:
return lowerMSABinaryIntr(Op, DAG, ISD::SHL);
+ case Intrinsic::mips_slli_b:
+ case Intrinsic::mips_slli_h:
+ case Intrinsic::mips_slli_w:
+ case Intrinsic::mips_slli_d:
+ return lowerMSABinaryImmIntr(Op, DAG, ISD::SHL,
+ lowerMSASplatImm(Op, 2, DAG));
case Intrinsic::mips_sra_b:
case Intrinsic::mips_sra_h:
case Intrinsic::mips_sra_w:
case Intrinsic::mips_sra_d:
return lowerMSABinaryIntr(Op, DAG, ISD::SRA);
+ case Intrinsic::mips_srai_b:
+ case Intrinsic::mips_srai_h:
+ case Intrinsic::mips_srai_w:
+ case Intrinsic::mips_srai_d:
+ return lowerMSABinaryImmIntr(Op, DAG, ISD::SRA,
+ lowerMSASplatImm(Op, 2, DAG));
case Intrinsic::mips_srl_b:
case Intrinsic::mips_srl_h:
case Intrinsic::mips_srl_w:
case Intrinsic::mips_srl_d:
return lowerMSABinaryIntr(Op, DAG, ISD::SRL);
+ case Intrinsic::mips_srli_b:
+ case Intrinsic::mips_srli_h:
+ case Intrinsic::mips_srli_w:
+ case Intrinsic::mips_srli_d:
+ return lowerMSABinaryImmIntr(Op, DAG, ISD::SRL,
+ lowerMSASplatImm(Op, 2, DAG));
case Intrinsic::mips_subv_b:
case Intrinsic::mips_subv_h:
case Intrinsic::mips_subv_w: