commit cff550995b2aef56a3c9956520249ac662df5696
author Dan Gohman <gohman@apple.com> Mon Nov 05 23:16:33 2007 +0000
committer Dan Gohman <gohman@apple.com> Mon Nov 05 23:16:33 2007 +0000
tree 8d03823ad57ae58ff7b9dea67eb0a45181715e51
parent f1ba1cad387dc52f3c2c5afc665edf9caad00992

Fix an abort in instcombine when folding creates a vector rem instruction.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@43743 91177308-0d34-0410-b5e6-96231b3b80d8

lib/Transforms/Scalar/InstructionCombining.cpp

diff --git a/lib/Transforms/Scalar/InstructionCombining.cpp b/lib/Transforms/Scalar/InstructionCombining.cpp
index 6ebf42a..c0ea28b 100644
--- a/lib/Transforms/Scalar/InstructionCombining.cpp
+++ b/lib/Transforms/Scalar/InstructionCombining.cpp
@@ -2622,6 +2622,7 @@
   if (I.getType()->isInteger()) {
     APInt Mask(APInt::getSignBit(I.getType()->getPrimitiveSizeInBits()));
     if (MaskedValueIsZero(Op1, Mask) && MaskedValueIsZero(Op0, Mask)) {
+      // X sdiv Y -> X udiv Y, iff X and Y don't have sign bit set
       return BinaryOperator::createUDiv(Op0, Op1, I.getName());
     }
   }      
@@ -2811,6 +2812,7 @@
 Instruction *InstCombiner::visitSRem(BinaryOperator &I) {
   Value *Op0 = I.getOperand(0), *Op1 = I.getOperand(1);
 
+  // Handle the integer rem common cases
   if (Instruction *common = commonIRemTransforms(I))
     return common;
   
@@ -2823,12 +2825,14 @@
       return &I;
     }
  
-  // If the top bits of both operands are zero (i.e. we can prove they are
+  // If the sign bits of both operands are zero (i.e. we can prove they are
   // unsigned inputs), turn this into a urem.
-  APInt Mask(APInt::getSignBit(I.getType()->getPrimitiveSizeInBits()));
-  if (MaskedValueIsZero(Op1, Mask) && MaskedValueIsZero(Op0, Mask)) {
-    // X srem Y -> X urem Y, iff X and Y don't have sign bit set
-    return BinaryOperator::createURem(Op0, Op1, I.getName());
+  if (I.getType()->isInteger()) {
+    APInt Mask(APInt::getSignBit(I.getType()->getPrimitiveSizeInBits()));
+    if (MaskedValueIsZero(Op1, Mask) && MaskedValueIsZero(Op0, Mask)) {
+      // X srem Y -> X urem Y, iff X and Y don't have sign bit set
+      return BinaryOperator::createURem(Op0, Op1, I.getName());
+    }
   }
 
   return 0;

test/Transforms/InstCombine/vector-srem.ll

diff --git a/test/Transforms/InstCombine/vector-srem.ll b/test/Transforms/InstCombine/vector-srem.ll
new file mode 100644
index 0000000..e8766eb
--- /dev/null
+++ b/test/Transforms/InstCombine/vector-srem.ll
@@ -0,0 +1,9 @@
+; RUN: llvm-as < %s | opt -instcombine | llvm-dis | grep {srem <4 x i32>}
+
+define <4 x i32> @foo(<4 x i32> %t, <4 x i32> %u)
+{
+  %k = sdiv <4 x i32> %t, %u
+  %l = mul <4 x i32> %k, %u
+  %m = sub <4 x i32> %t, %l
+  ret <4 x i32> %m
+}