More renamings of Target/Machine*Info to Target/Target*Info


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@5204 91177308-0d34-0410-b5e6-96231b3b80d8
diff --git a/lib/CodeGen/InstrSched/InstrScheduling.cpp b/lib/CodeGen/InstrSched/InstrScheduling.cpp
index 278e7ad..fe5047b 100644
--- a/lib/CodeGen/InstrSched/InstrScheduling.cpp
+++ b/lib/CodeGen/InstrSched/InstrScheduling.cpp
@@ -340,8 +340,8 @@
 
 class SchedulingManager: public NonCopyable {
 public: // publicly accessible data members
-  const unsigned int nslots;
-  const MachineSchedInfo& schedInfo;
+  const unsigned nslots;
+  const TargetSchedInfo& schedInfo;
   SchedPriorities& schedPrio;
   InstrSchedule isched;
   
diff --git a/lib/CodeGen/InstrSched/SchedGraph.cpp b/lib/CodeGen/InstrSched/SchedGraph.cpp
index 4b9ff1b..7094068 100644
--- a/lib/CodeGen/InstrSched/SchedGraph.cpp
+++ b/lib/CodeGen/InstrSched/SchedGraph.cpp
@@ -10,7 +10,7 @@
 #include "llvm/CodeGen/InstrSelection.h"
 #include "llvm/CodeGen/MachineCodeForInstruction.h"
 #include "llvm/CodeGen/MachineFunction.h"
-#include "llvm/Target/MachineRegInfo.h"
+#include "llvm/Target/TargetRegInfo.h"
 #include "llvm/Target/TargetMachine.h"
 #include "llvm/Target/MachineInstrInfo.h"
 #include "llvm/Function.h"
diff --git a/lib/CodeGen/InstrSched/SchedPriorities.h b/lib/CodeGen/InstrSched/SchedPriorities.h
index 2b9405d..62e41ee 100644
--- a/lib/CodeGen/InstrSched/SchedPriorities.h
+++ b/lib/CodeGen/InstrSched/SchedPriorities.h
@@ -15,7 +15,7 @@
 
 #include "SchedGraph.h"
 #include "llvm/CodeGen/InstrScheduling.h"
-#include "llvm/Target/MachineSchedInfo.h"
+#include "llvm/Target/TargetSchedInfo.h"
 #include "Support/hash_set"
 #include <list>
 
diff --git a/lib/CodeGen/InstrSelection/InstrSelection.cpp b/lib/CodeGen/InstrSelection/InstrSelection.cpp
index c7bf70c..294ecc6 100644
--- a/lib/CodeGen/InstrSelection/InstrSelection.cpp
+++ b/lib/CodeGen/InstrSelection/InstrSelection.cpp
@@ -12,7 +12,7 @@
 #include "llvm/CodeGen/InstrForest.h"
 #include "llvm/CodeGen/MachineCodeForInstruction.h"
 #include "llvm/CodeGen/MachineFunction.h"
-#include "llvm/Target/MachineRegInfo.h"
+#include "llvm/Target/TargetRegInfo.h"
 #include "llvm/Target/TargetMachine.h"
 #include "llvm/Function.h"
 #include "llvm/iPHINode.h"
diff --git a/lib/CodeGen/InstrSelection/InstrSelectionSupport.cpp b/lib/CodeGen/InstrSelection/InstrSelectionSupport.cpp
index 86dde07..d7cb439 100644
--- a/lib/CodeGen/InstrSelection/InstrSelectionSupport.cpp
+++ b/lib/CodeGen/InstrSelection/InstrSelectionSupport.cpp
@@ -13,7 +13,7 @@
 #include "llvm/CodeGen/MachineFunction.h"
 #include "llvm/CodeGen/InstrForest.h"
 #include "llvm/Target/TargetMachine.h"
-#include "llvm/Target/MachineRegInfo.h"
+#include "llvm/Target/TargetRegInfo.h"
 #include "llvm/Target/MachineInstrInfo.h"
 #include "llvm/Constants.h"
 #include "llvm/Function.h"
diff --git a/lib/CodeGen/RegAlloc/LiveRangeInfo.h b/lib/CodeGen/RegAlloc/LiveRangeInfo.h
index 05e9aa8..71fda16 100644
--- a/lib/CodeGen/RegAlloc/LiveRangeInfo.h
+++ b/lib/CodeGen/RegAlloc/LiveRangeInfo.h
@@ -25,7 +25,7 @@
 class LiveRange;
 class MachineInstr;
 class RegClass;
-class MachineRegInfo;
+class TargetRegInfo;
 class TargetMachine;
 class Value;
 class Function;
@@ -50,7 +50,7 @@
 
   std::vector<RegClass *> & RegClassList;// vector containing register classess
 
-  const MachineRegInfo& MRI;        // machine reg info
+  const TargetRegInfo& MRI;        // machine reg info
 
   std::vector<MachineInstr*> CallRetInstrList;  // a list of all call/ret instrs
 
diff --git a/lib/CodeGen/RegAlloc/PhyRegAlloc.h b/lib/CodeGen/RegAlloc/PhyRegAlloc.h
index c84ca03..ea4f562 100644
--- a/lib/CodeGen/RegAlloc/PhyRegAlloc.h
+++ b/lib/CodeGen/RegAlloc/PhyRegAlloc.h
@@ -7,9 +7,9 @@
    =====
 
  * RegisterClasses: Each RegClass accepts a 
-   MachineRegClass which contains machine specific info about that register
+   TargetRegClass which contains machine specific info about that register
    class. The code in the RegClass is machine independent and they use
-   access functions in the MachineRegClass object passed into it to get
+   access functions in the TargetRegClass object passed into it to get
    machine specific info.
 
  * Machine dependent work: All parts of the register coloring algorithm
@@ -24,7 +24,7 @@
 #include <map>
 
 class MachineFunction;
-class MachineRegInfo;
+class TargetRegInfo;
 class FunctionLiveVarInfo;
 class MachineInstr;
 class LoopInfo;
@@ -57,7 +57,7 @@
   FunctionLiveVarInfo *const LVI;       // LV information for this method 
                                         // (already computed for BBs) 
   LiveRangeInfo LRI;                    // LR info  (will be computed)
-  const MachineRegInfo &MRI;            // Machine Register information
+  const TargetRegInfo &MRI;             // Machine Register information
   const unsigned NumOfRegClasses;       // recorded here for efficiency
 
   
diff --git a/lib/CodeGen/RegAlloc/RegClass.cpp b/lib/CodeGen/RegAlloc/RegClass.cpp
index 65716cf..90d3987 100644
--- a/lib/CodeGen/RegAlloc/RegClass.cpp
+++ b/lib/CodeGen/RegAlloc/RegClass.cpp
@@ -14,7 +14,7 @@
 // createInterferenceGraph() above.
 //----------------------------------------------------------------------------
 RegClass::RegClass(const Function *M, 
-		   const MachineRegClassInfo *Mrc,
+		   const TargetRegClassInfo *Mrc,
 		   const ReservedColorListType *RCL)
                   :  Meth(M), MRC(Mrc), RegClassID( Mrc->getRegClassID() ),
                      IG(this), IGNodeStack(), ReservedColorList(RCL) {
diff --git a/lib/CodeGen/RegAlloc/RegClass.h b/lib/CodeGen/RegAlloc/RegClass.h
index 99a84c0..7e2103c 100644
--- a/lib/CodeGen/RegAlloc/RegClass.h
+++ b/lib/CodeGen/RegAlloc/RegClass.h
@@ -9,9 +9,9 @@
 #define REG_CLASS_H
 
 #include "llvm/CodeGen/InterferenceGraph.h"
-#include "llvm/Target/MachineRegInfo.h"
+#include "llvm/Target/TargetRegInfo.h"
 #include <stack>
-class MachineRegClassInfo;
+class TargetRegClassInfo;
 
 typedef std::vector<unsigned> ReservedColorListType;
 
@@ -24,7 +24,7 @@
 //   This is the class that contains all data structures and common algos
 //   for coloring a particular register class (e.g., int class, fp class).  
 //   This class is hardware independent. This class accepts a hardware 
-//   dependent description of machine registers (MachineRegInfo class) to 
+//   dependent description of machine registers (TargetRegInfo class) to 
 //   get hardware specific info and to color an individual IG node.
 //
 //   This class contains the InterferenceGraph (IG).
@@ -35,7 +35,7 @@
 //-----------------------------------------------------------------------------
 class RegClass {
   const Function *const Meth;           // Function we are working on
-  const MachineRegClassInfo *const MRC; // corresponding MRC
+  const TargetRegClassInfo *const MRC; // corresponding MRC
   const unsigned RegClassID;            // my int ID
 
   InterferenceGraph IG;                 // Interference graph - constructed by
@@ -69,7 +69,7 @@
  public:
 
   RegClass(const Function *M,
-	   const MachineRegClassInfo *MRC,
+	   const TargetRegClassInfo *MRC,
 	   const ReservedColorListType *RCL = 0);
 
   inline void createInterferenceGraph() { IG.createGraph(); }