commit d10fd9791c20fd8368fa0ce94b626b769c6c8ba0
author Owen Anderson <resistor@mac.com> Mon Dec 31 06:32:00 2007 +0000
committer Owen Anderson <resistor@mac.com> Mon Dec 31 06:32:00 2007 +0000
tree 15d4f8237ffa7600737fab617923b5bef3267b16
parent f20c1a497fe3922ac718429d65a5fe396890575e

Move copyRegToReg from MRegisterInfo to TargetInstrInfo.  This is part of the
Machine-level API cleanup instigated by Chris.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45470 91177308-0d34-0410-b5e6-96231b3b80d8

lib/CodeGen/LowerSubregs.cpp

diff --git a/lib/CodeGen/LowerSubregs.cpp b/lib/CodeGen/LowerSubregs.cpp
index 668a9e5..4172b12 100644
--- a/lib/CodeGen/LowerSubregs.cpp
+++ b/lib/CodeGen/LowerSubregs.cpp
@@ -63,6 +63,7 @@
    MachineBasicBlock *MBB = MI->getParent();
    MachineFunction &MF = *MBB->getParent();
    const MRegisterInfo &MRI = *MF.getTarget().getRegisterInfo();
+   const TargetInstrInfo &TII = *MF.getTarget().getInstrInfo();
    
    assert(MI->getOperand(0).isRegister() && MI->getOperand(0).isDef() &&
           MI->getOperand(1).isRegister() && MI->getOperand(1).isUse() &&
@@ -88,7 +89,7 @@
      assert(TRC == getPhysicalRegisterRegClass(MRI, SrcReg) &&
              "Extract subreg and Dst must be of same register class");
 
-     MRI.copyRegToReg(*MBB, MI, DstReg, SrcReg, TRC, TRC);
+     TII.copyRegToReg(*MBB, MI, DstReg, SrcReg, TRC, TRC);
      MachineBasicBlock::iterator dMI = MI;
      DOUT << "subreg: " << *(--dMI);
    }
@@ -103,6 +104,7 @@
   MachineBasicBlock *MBB = MI->getParent();
   MachineFunction &MF = *MBB->getParent();
   const MRegisterInfo &MRI = *MF.getTarget().getRegisterInfo(); 
+  const TargetInstrInfo &TII = *MF.getTarget().getInstrInfo();
   unsigned DstReg = 0;
   unsigned SrcReg = 0;
   unsigned InsReg = 0;
@@ -157,7 +159,7 @@
       } else {
         TRC1 = MF.getRegInfo().getRegClass(InsReg);
       }
-      MRI.copyRegToReg(*MBB, MI, DstSubReg, InsReg, TRC1, TRC1);
+      TII.copyRegToReg(*MBB, MI, DstSubReg, InsReg, TRC1, TRC1);
 
 #ifndef NDEBUG
       MachineBasicBlock::iterator dMI = MI;
@@ -184,7 +186,7 @@
     assert(TRC0 == getPhysicalRegisterRegClass(MRI, SrcReg) &&
             "Insert superreg and Dst must be of same register class");
 
-    MRI.copyRegToReg(*MBB, MI, DstReg, SrcReg, TRC0, TRC0);
+    TII.copyRegToReg(*MBB, MI, DstReg, SrcReg, TRC0, TRC0);
 
 #ifndef NDEBUG
     MachineBasicBlock::iterator dMI = MI;
@@ -206,7 +208,7 @@
     } else {
       TRC1 = MF.getRegInfo().getRegClass(InsReg);
     }
-    MRI.copyRegToReg(*MBB, MI, DstSubReg, InsReg, TRC1, TRC1);
+    TII.copyRegToReg(*MBB, MI, DstSubReg, InsReg, TRC1, TRC1);
 
 #ifndef NDEBUG
     MachineBasicBlock::iterator dMI = MI;