commit d248652b8beaef52b1b256fa52092967f1b0f6ef
author Vikram S. Adve <vadve@cs.uiuc.edu> Tue Oct 21 12:29:45 2003 +0000
committer Vikram S. Adve <vadve@cs.uiuc.edu> Tue Oct 21 12:29:45 2003 +0000
tree 0a42b916ec3d7442d3aeb8054f1bbd3d91f87798
parent 472c3046fe7b12fa9e8dd4c1bd98d0efad51e7f8

When opcodes like ADD were split into reg. and immed. versions (ADDi and ADDr),
this code wasn't fixed correctly so it missed copy operations that used ADDi.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@9318 91177308-0d34-0410-b5e6-96231b3b80d8

lib/Target/SparcV9/SparcV9PeepholeOpts.cpp

diff --git a/lib/Target/SparcV9/SparcV9PeepholeOpts.cpp b/lib/Target/SparcV9/SparcV9PeepholeOpts.cpp
index 2b22558..9d50f35 100644
--- a/lib/Target/SparcV9/SparcV9PeepholeOpts.cpp
+++ b/lib/Target/SparcV9/SparcV9PeepholeOpts.cpp
@@ -63,7 +63,8 @@
     return (/* both operands are allocated to the same register */
             MI->getOperand(0).getAllocatedRegNum() == 
             MI->getOperand(1).getAllocatedRegNum());
-  } else if (MI->getOpCode() == V9::ADDr || MI->getOpCode() == V9::ORr) {
+  } else if (MI->getOpCode() == V9::ADDr || MI->getOpCode() == V9::ORr ||
+             MI->getOpCode() == V9::ADDi || MI->getOpCode() == V9::ORi) {
     unsigned srcWithDestReg;
     
     for (srcWithDestReg = 0; srcWithDestReg < 2; ++srcWithDestReg)