commit d27c991cebe48fdf82b5d9eec6c2a1a244f82622
author Chris Lattner <sabre@nondot.org> Sun Mar 30 18:22:13 2008 +0000
committer Chris Lattner <sabre@nondot.org> Sun Mar 30 18:22:13 2008 +0000
tree 540c5d6ba547c04eee48f2e86ce4f39ffd0c26ed
parent f19f58a9360927f8ef50b9a029e8efb780d3d8a8

Fix "Control reaches the end of non-void function" warnings, 
patch by David Chisnall.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48963 91177308-0d34-0410-b5e6-96231b3b80d8

lib/Target/ARM/ARMInstrInfo.cpp

diff --git a/lib/Target/ARM/ARMInstrInfo.cpp b/lib/Target/ARM/ARMInstrInfo.cpp
index 35d6313..10328f7 100644
--- a/lib/Target/ARM/ARMInstrInfo.cpp
+++ b/lib/Target/ARM/ARMInstrInfo.cpp
@@ -919,6 +919,7 @@
     }
   }
   }
+  return 0; // Not reached
 }
 
 /// GetFunctionSize - Returns the size of the specified MachineFunction.

lib/Target/Alpha/AlphaInstrInfo.cpp

diff --git a/lib/Target/Alpha/AlphaInstrInfo.cpp b/lib/Target/Alpha/AlphaInstrInfo.cpp
index 48e23f9..96a75a6 100644
--- a/lib/Target/Alpha/AlphaInstrInfo.cpp
+++ b/lib/Target/Alpha/AlphaInstrInfo.cpp
@@ -307,6 +307,7 @@
   default:
     assert(0 && "Unknown opcode");
   }
+  return 0; // Not reached
 }
 
 // Branch analysis.

lib/Target/MSIL/MSILWriter.cpp

diff --git a/lib/Target/MSIL/MSILWriter.cpp b/lib/Target/MSIL/MSILWriter.cpp
index f0a6684..187dd4a 100644
--- a/lib/Target/MSIL/MSILWriter.cpp
+++ b/lib/Target/MSIL/MSILWriter.cpp
@@ -259,6 +259,7 @@
     cerr << "CallingConvID = " << CallingConvID << '\n';
     assert(0 && "Unsupported calling convention");
   }
+  return ""; // Not reached
 }
 
 
@@ -304,6 +305,7 @@
     cerr << "Type = " << *Ty << '\n';
     assert(0 && "Invalid primitive type");
   }
+  return ""; // Not reached
 }
 
 
@@ -331,6 +333,7 @@
     cerr << "Type = " << *Ty << '\n';
     assert(0 && "Invalid type in getTypeName()");
   }
+  return ""; // Not reached
 }
 
 
@@ -374,6 +377,7 @@
     cerr << "TypeID = " << Ty->getTypeID() << '\n';
     assert(0 && "Invalid type in TypeToPostfix()");
   }
+  return ""; // Not reached
 }
 
 
@@ -1446,6 +1450,7 @@
     cerr << "Bits = " << N << '\n';
     assert(0 && "Unsupported integer width");
   }
+  return 0; // Not reached
 }
 
 

lib/Target/Mips/MipsISelLowering.cpp

diff --git a/lib/Target/Mips/MipsISelLowering.cpp b/lib/Target/Mips/MipsISelLowering.cpp
index 453082c..5c2e1c0 100644
--- a/lib/Target/Mips/MipsISelLowering.cpp
+++ b/lib/Target/Mips/MipsISelLowering.cpp
@@ -181,6 +181,7 @@
 LowerGlobalTLSAddress(SDOperand Op, SelectionDAG &DAG)
 {
   assert(0 && "TLS not implemented for MIPS.");
+  return SDOperand(); // Not reached
 }
 
 SDOperand MipsTargetLowering::

lib/Target/Mips/MipsRegisterInfo.cpp

diff --git a/lib/Target/Mips/MipsRegisterInfo.cpp b/lib/Target/Mips/MipsRegisterInfo.cpp
index 4ca5ade..fd04153 100644
--- a/lib/Target/Mips/MipsRegisterInfo.cpp
+++ b/lib/Target/Mips/MipsRegisterInfo.cpp
@@ -81,6 +81,7 @@
     case Mips::RA   : return 31;
     default: assert(0 && "Unknown register number!");
   }    
+  return 0; // Not reached
 }
 
 void MipsRegisterInfo::reMaterialize(MachineBasicBlock &MBB, 

lib/Target/PowerPC/PPCISelLowering.cpp

diff --git a/lib/Target/PowerPC/PPCISelLowering.cpp b/lib/Target/PowerPC/PPCISelLowering.cpp
index dff53cd..f307184 100644
--- a/lib/Target/PowerPC/PPCISelLowering.cpp
+++ b/lib/Target/PowerPC/PPCISelLowering.cpp
@@ -1104,6 +1104,7 @@
 SDOperand PPCTargetLowering::LowerGlobalTLSAddress(SDOperand Op, 
                                                    SelectionDAG &DAG) {
   assert(0 && "TLS not implemented for PPC.");
+  return SDOperand(); // Not reached
 }
 
 SDOperand PPCTargetLowering::LowerGlobalAddress(SDOperand Op, 
@@ -1197,6 +1198,7 @@
                               const PPCSubtarget &Subtarget) {
   
   assert(0 && "VAARG in ELF32 ABI not implemented yet!");
+  return SDOperand(); // Not reached
 }
 
 SDOperand PPCTargetLowering::LowerVASTART(SDOperand Op, SelectionDAG &DAG,