| commit | d3355e22a7e5a2bb1254a4ac18f81175cab40a2e | [log] [tgz] |
|---|---|---|
| author | Andrew Lenharth <andrewl@lenharth.org> | Thu Apr 07 20:11:32 2005 +0000 |
| committer | Andrew Lenharth <andrewl@lenharth.org> | Thu Apr 07 20:11:32 2005 +0000 |
| tree | 91d97dc17c809ea796af9493d66f6d00b0fff3b3 | |
| parent | 5a6bace3ab8db44e5412a773626fbb76fb316767 [diff] [blame] |
Alpha zero extends setcc results git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21149 91177308-0d34-0410-b5e6-96231b3b80d8
diff --git a/lib/Target/Alpha/AlphaISelPattern.cpp b/lib/Target/Alpha/AlphaISelPattern.cpp index 381ecdd..8d6c46a 100644 --- a/lib/Target/Alpha/AlphaISelPattern.cpp +++ b/lib/Target/Alpha/AlphaISelPattern.cpp
@@ -53,6 +53,7 @@ //I am having problems with shr n ubyte 1 setShiftAmountType(MVT::i64); setSetCCResultType(MVT::i64); + setSetCCResultContents(ZeroOrOneSetCCResult); addRegisterClass(MVT::i64, Alpha::GPRCRegisterClass); addRegisterClass(MVT::f64, Alpha::FPRCRegisterClass);