switch CMOVBE to the multipattern:
21 insertions(+), 53 deletions(-)
Moar change coming before I switch the rest.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115697 91177308-0d34-0410-b5e6-96231b3b80d8
diff --git a/lib/Target/X86/X86ISelDAGToDAG.cpp b/lib/Target/X86/X86ISelDAGToDAG.cpp
index 018ea9e..048c7bb 100644
--- a/lib/Target/X86/X86ISelDAGToDAG.cpp
+++ b/lib/Target/X86/X86ISelDAGToDAG.cpp
@@ -1538,9 +1538,9 @@
case X86::CMOVB16rr: case X86::CMOVB16rm:
case X86::CMOVB32rr: case X86::CMOVB32rm:
case X86::CMOVB64rr: case X86::CMOVB64rm:
- case X86::CMOVBE16rr: case X86::CMOVBE16rm:
- case X86::CMOVBE32rr: case X86::CMOVBE32rm:
- case X86::CMOVBE64rr: case X86::CMOVBE64rm:
+ case X86::CMOVBErr16: case X86::CMOVBErm16:
+ case X86::CMOVBErr32: case X86::CMOVBErm32:
+ case X86::CMOVBErr64: case X86::CMOVBErm64:
case X86::CMOVE16rr: case X86::CMOVE16rm:
case X86::CMOVE32rr: case X86::CMOVE32rm:
case X86::CMOVE64rr: case X86::CMOVE64rm:
diff --git a/lib/Target/X86/X86InstrCMovSetCC.td b/lib/Target/X86/X86InstrCMovSetCC.td
index 9853a0c..c0df8ac 100644
--- a/lib/Target/X86/X86InstrCMovSetCC.td
+++ b/lib/Target/X86/X86InstrCMovSetCC.td
@@ -50,7 +50,9 @@
} // Uses = [EFLAGS], Predicates = [HasCMov], Constraints = "$src1 = $dst"
} // end multiclass
-//defm CMOVBE : CMOV<0x46, "cmovbe", X86_COND_BE>;
+
+// Conditional Moves.
+defm CMOVBE : CMOV<0x46, "cmovbe", X86_COND_BE>;
let Constraints = "$src1 = $dst" in {
@@ -108,18 +110,6 @@
[(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
X86_COND_NE, EFLAGS))]>,
TB;
-def CMOVBE16rr: I<0x46, MRMSrcReg, // if <=u, GR16 = GR16
- (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
- "cmovbe{w}\t{$src2, $dst|$dst, $src2}",
- [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
- X86_COND_BE, EFLAGS))]>,
- TB, OpSize;
-def CMOVBE32rr: I<0x46, MRMSrcReg, // if <=u, GR32 = GR32
- (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
- "cmovbe{l}\t{$src2, $dst|$dst, $src2}",
- [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
- X86_COND_BE, EFLAGS))]>,
- TB;
def CMOVA16rr : I<0x47, MRMSrcReg, // if >u, GR16 = GR16
(outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
"cmova{w}\t{$src2, $dst|$dst, $src2}",
@@ -302,18 +292,6 @@
[(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
X86_COND_NE, EFLAGS))]>,
TB;
-def CMOVBE16rm: I<0x46, MRMSrcMem, // if <=u, GR16 = [mem16]
- (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
- "cmovbe{w}\t{$src2, $dst|$dst, $src2}",
- [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
- X86_COND_BE, EFLAGS))]>,
- TB, OpSize;
-def CMOVBE32rm: I<0x46, MRMSrcMem, // if <=u, GR32 = [mem32]
- (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
- "cmovbe{l}\t{$src2, $dst|$dst, $src2}",
- [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
- X86_COND_BE, EFLAGS))]>,
- TB;
def CMOVA16rm : I<0x47, MRMSrcMem, // if >u, GR16 = [mem16]
(outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
"cmova{w}\t{$src2, $dst|$dst, $src2}",
@@ -523,11 +501,6 @@
"cmovne{q}\t{$src2, $dst|$dst, $src2}",
[(set GR64:$dst, (X86cmov GR64:$src1, GR64:$src2,
X86_COND_NE, EFLAGS))]>, TB;
-def CMOVBE64rr: RI<0x46, MRMSrcReg, // if <=u, GR64 = GR64
- (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
- "cmovbe{q}\t{$src2, $dst|$dst, $src2}",
- [(set GR64:$dst, (X86cmov GR64:$src1, GR64:$src2,
- X86_COND_BE, EFLAGS))]>, TB;
def CMOVA64rr : RI<0x47, MRMSrcReg, // if >u, GR64 = GR64
(outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
"cmova{q}\t{$src2, $dst|$dst, $src2}",
@@ -605,11 +578,6 @@
"cmovne{q}\t{$src2, $dst|$dst, $src2}",
[(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2),
X86_COND_NE, EFLAGS))]>, TB;
-def CMOVBE64rm: RI<0x46, MRMSrcMem, // if <=u, GR64 = [mem64]
- (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
- "cmovbe{q}\t{$src2, $dst|$dst, $src2}",
- [(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2),
- X86_COND_BE, EFLAGS))]>, TB;
def CMOVA64rm : RI<0x47, MRMSrcMem, // if >u, GR64 = [mem64]
(outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
"cmova{q}\t{$src2, $dst|$dst, $src2}",
diff --git a/lib/Target/X86/X86InstrCompiler.td b/lib/Target/X86/X86InstrCompiler.td
index 9af6218..2c0cbc0 100644
--- a/lib/Target/X86/X86InstrCompiler.td
+++ b/lib/Target/X86/X86InstrCompiler.td
@@ -871,9 +871,9 @@
def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_BE, EFLAGS),
(CMOVA32rm GR32:$src2, addr:$src1)>;
def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_A, EFLAGS),
- (CMOVBE16rm GR16:$src2, addr:$src1)>;
+ (CMOVBErm16 GR16:$src2, addr:$src1)>;
def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_A, EFLAGS),
- (CMOVBE32rm GR32:$src2, addr:$src1)>;
+ (CMOVBErm32 GR32:$src2, addr:$src1)>;
def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_L, EFLAGS),
(CMOVGE16rm GR16:$src2, addr:$src1)>;
def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_L, EFLAGS),
@@ -926,7 +926,7 @@
def : Pat<(X86cmov (loadi64 addr:$src1), GR64:$src2, X86_COND_BE, EFLAGS),
(CMOVA64rm GR64:$src2, addr:$src1)>;
def : Pat<(X86cmov (loadi64 addr:$src1), GR64:$src2, X86_COND_A, EFLAGS),
- (CMOVBE64rm GR64:$src2, addr:$src1)>;
+ (CMOVBErm64 GR64:$src2, addr:$src1)>;
def : Pat<(X86cmov (loadi64 addr:$src1), GR64:$src2, X86_COND_L, EFLAGS),
(CMOVGE64rm GR64:$src2, addr:$src1)>;
def : Pat<(X86cmov (loadi64 addr:$src1), GR64:$src2, X86_COND_GE, EFLAGS),
diff --git a/lib/Target/X86/X86InstrInfo.cpp b/lib/Target/X86/X86InstrInfo.cpp
index dd4940b..14382d7 100644
--- a/lib/Target/X86/X86InstrInfo.cpp
+++ b/lib/Target/X86/X86InstrInfo.cpp
@@ -482,9 +482,9 @@
{ X86::CMOVB16rr, X86::CMOVB16rm, 0 },
{ X86::CMOVB32rr, X86::CMOVB32rm, 0 },
{ X86::CMOVB64rr, X86::CMOVB64rm, 0 },
- { X86::CMOVBE16rr, X86::CMOVBE16rm, 0 },
- { X86::CMOVBE32rr, X86::CMOVBE32rm, 0 },
- { X86::CMOVBE64rr, X86::CMOVBE64rm, 0 },
+ { X86::CMOVBErr16, X86::CMOVBErm16, 0 },
+ { X86::CMOVBErr32, X86::CMOVBErm32, 0 },
+ { X86::CMOVBErr64, X86::CMOVBErm64, 0 },
{ X86::CMOVE16rr, X86::CMOVE16rm, 0 },
{ X86::CMOVE32rr, X86::CMOVE32rm, 0 },
{ X86::CMOVE64rr, X86::CMOVE64rm, 0 },
@@ -1445,9 +1445,9 @@
case X86::CMOVNE16rr:
case X86::CMOVNE32rr:
case X86::CMOVNE64rr:
- case X86::CMOVBE16rr:
- case X86::CMOVBE32rr:
- case X86::CMOVBE64rr:
+ case X86::CMOVBErr16:
+ case X86::CMOVBErr32:
+ case X86::CMOVBErr64:
case X86::CMOVA16rr:
case X86::CMOVA32rr:
case X86::CMOVA64rr:
@@ -1496,12 +1496,12 @@
case X86::CMOVNE16rr: Opc = X86::CMOVE16rr; break;
case X86::CMOVNE32rr: Opc = X86::CMOVE32rr; break;
case X86::CMOVNE64rr: Opc = X86::CMOVE64rr; break;
- case X86::CMOVBE16rr: Opc = X86::CMOVA16rr; break;
- case X86::CMOVBE32rr: Opc = X86::CMOVA32rr; break;
- case X86::CMOVBE64rr: Opc = X86::CMOVA64rr; break;
- case X86::CMOVA16rr: Opc = X86::CMOVBE16rr; break;
- case X86::CMOVA32rr: Opc = X86::CMOVBE32rr; break;
- case X86::CMOVA64rr: Opc = X86::CMOVBE64rr; break;
+ case X86::CMOVBErr16: Opc = X86::CMOVA16rr; break;
+ case X86::CMOVBErr32: Opc = X86::CMOVA32rr; break;
+ case X86::CMOVBErr64: Opc = X86::CMOVA64rr; break;
+ case X86::CMOVA16rr: Opc = X86::CMOVBErr16; break;
+ case X86::CMOVA32rr: Opc = X86::CMOVBErr32; break;
+ case X86::CMOVA64rr: Opc = X86::CMOVBErr64; break;
case X86::CMOVL16rr: Opc = X86::CMOVGE16rr; break;
case X86::CMOVL32rr: Opc = X86::CMOVGE32rr; break;
case X86::CMOVL64rr: Opc = X86::CMOVGE64rr; break;