| commit | d56aa55358689dac47b774c6778363367f0158b4 | [log] [tgz] |
|---|---|---|
| author | Andrew Lenharth <andrewl@lenharth.org> | Thu May 18 17:29:34 2006 +0000 |
| committer | Andrew Lenharth <andrewl@lenharth.org> | Thu May 18 17:29:34 2006 +0000 |
| tree | b1d847cd46b0d27e01078b97d9f2591d7a128ead | |
| parent | 751458dac9fec1c9436065a6e1ea0dd0a9cf3ec3 [diff] [blame] |
Fix a bogus gcc warning git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28382 91177308-0d34-0410-b5e6-96231b3b80d8
diff --git a/lib/Target/Alpha/AlphaISelDAGToDAG.cpp b/lib/Target/Alpha/AlphaISelDAGToDAG.cpp index b4c7feb..772da03 100644 --- a/lib/Target/Alpha/AlphaISelDAGToDAG.cpp +++ b/lib/Target/Alpha/AlphaISelDAGToDAG.cpp
@@ -377,8 +377,8 @@ break; case ISD::AND: { - ConstantSDNode* SC; - ConstantSDNode* MC; + ConstantSDNode* SC = NULL; + ConstantSDNode* MC = NULL; if (N->getOperand(0).getOpcode() == ISD::SRL && (MC = dyn_cast<ConstantSDNode>(N->getOperand(1))) && (SC = dyn_cast<ConstantSDNode>(N->getOperand(0).getOperand(1))))