commit d597263b9442923bacc24f26a8510fb69f992864
author Akira Hatanaka <ahatanaka@mips.com> Mon Apr 22 19:58:23 2013 +0000
committer Akira Hatanaka <ahatanaka@mips.com> Mon Apr 22 19:58:23 2013 +0000
tree 701478fef64be3c439f5d1cd02ef6054003fe009
parent 6804971dcfbba1dcf7b0f8335588ba2ab6b0f073

[mips] In performDSPShiftCombine, check that all elements in the vector are
shifted by the same amount and the shift amount is smaller than the element
size.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180039 91177308-0d34-0410-b5e6-96231b3b80d8

lib/Target/Mips/MipsDSPInstrInfo.td

diff --git a/lib/Target/Mips/MipsDSPInstrInfo.td b/lib/Target/Mips/MipsDSPInstrInfo.td
index 6790a27..23c6a05 100644
--- a/lib/Target/Mips/MipsDSPInstrInfo.td
+++ b/lib/Target/Mips/MipsDSPInstrInfo.td
@@ -1288,18 +1288,18 @@
 
 // Shift immediate patterns.
 class DSPShiftPat<Instruction Inst, ValueType ValTy, SDPatternOperator Node,
-                  ImmLeaf Imm, Predicate Pred = HasDSP> :
+                  SDPatternOperator Imm, Predicate Pred = HasDSP> :
   DSPPat<(Node ValTy:$a, Imm:$shamt), (Inst ValTy:$a, Imm:$shamt), Pred>;
 
-def : DSPShiftPat<SHLL_PH, v2i16, MipsSHLL_DSP, immZExt4>;
-def : DSPShiftPat<SHRA_PH, v2i16, MipsSHRA_DSP, immZExt4>;
-def : DSPShiftPat<SHRL_PH, v2i16, MipsSHRL_DSP, immZExt4, HasDSPR2>;
+def : DSPShiftPat<SHLL_PH, v2i16, MipsSHLL_DSP, imm>;
+def : DSPShiftPat<SHRA_PH, v2i16, MipsSHRA_DSP, imm>;
+def : DSPShiftPat<SHRL_PH, v2i16, MipsSHRL_DSP, imm, HasDSPR2>;
 def : DSPShiftPat<SHLL_PH, v2i16, int_mips_shll_ph, immZExt4>;
 def : DSPShiftPat<SHRA_PH, v2i16, int_mips_shra_ph, immZExt4>;
 def : DSPShiftPat<SHRL_PH, v2i16, int_mips_shrl_ph, immZExt4, HasDSPR2>;
-def : DSPShiftPat<SHLL_QB, v4i8, MipsSHLL_DSP, immZExt3>;
-def : DSPShiftPat<SHRA_QB, v4i8, MipsSHRA_DSP, immZExt3, HasDSPR2>;
-def : DSPShiftPat<SHRL_QB, v4i8, MipsSHRL_DSP, immZExt3>;
+def : DSPShiftPat<SHLL_QB, v4i8, MipsSHLL_DSP, imm>;
+def : DSPShiftPat<SHRA_QB, v4i8, MipsSHRA_DSP, imm, HasDSPR2>;
+def : DSPShiftPat<SHRL_QB, v4i8, MipsSHRL_DSP, imm>;
 def : DSPShiftPat<SHLL_QB, v4i8, int_mips_shll_qb, immZExt3>;
 def : DSPShiftPat<SHRA_QB, v4i8, int_mips_shra_qb, immZExt3, HasDSPR2>;
 def : DSPShiftPat<SHRL_QB, v4i8, int_mips_shrl_qb, immZExt3>;

lib/Target/Mips/MipsSEISelLowering.cpp

diff --git a/lib/Target/Mips/MipsSEISelLowering.cpp b/lib/Target/Mips/MipsSEISelLowering.cpp
index ca911f0..23d2578 100644
--- a/lib/Target/Mips/MipsSEISelLowering.cpp
+++ b/lib/Target/Mips/MipsSEISelLowering.cpp
@@ -327,9 +327,11 @@
   unsigned EltSize = Ty.getVectorElementType().getSizeInBits();
   BuildVectorSDNode *BV = dyn_cast<BuildVectorSDNode>(N->getOperand(1));
 
-  if (!BV || !BV->isConstantSplat(SplatValue, SplatUndef, SplatBitSize,
-                                  HasAnyUndefs, EltSize,
-                                  !Subtarget->isLittle()))
+  if (!BV ||
+      !BV->isConstantSplat(SplatValue, SplatUndef, SplatBitSize, HasAnyUndefs, EltSize,
+                           !Subtarget->isLittle()) ||
+      (SplatBitSize != EltSize) ||
+      !isUIntN(Log2_32(EltSize), SplatValue.getZExtValue()))
     return SDValue();
 
   return DAG.getNode(Opc, N->getDebugLoc(), Ty, N->getOperand(0),