diff --git a/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp b/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
index 38e0d42..7bb4ce2 100644
--- a/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
+++ b/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
@@ -405,8 +405,9 @@
   case ISD::CopyFromReg:
     Tmp1 = LegalizeOp(Node->getOperand(0));
     if (Tmp1 != Node->getOperand(0))
-      Result = DAG.getCopyFromReg(cast<RegSDNode>(Node)->getReg(),
-                                  Node->getValueType(0), Tmp1);
+      Result = DAG.getCopyFromReg(Tmp1, 
+                            cast<RegisterSDNode>(Node->getOperand(1))->getReg(),
+                                  Node->getValueType(0));
     else
       Result = Op.getValue(0);
 
@@ -418,7 +419,8 @@
   case ISD::ImplicitDef:
     Tmp1 = LegalizeOp(Node->getOperand(0));
     if (Tmp1 != Node->getOperand(0))
-      Result = DAG.getImplicitDef(Tmp1, cast<RegSDNode>(Node)->getReg());
+      Result = DAG.getNode(ISD::ImplicitDef, MVT::Other,
+                           Tmp1, Node->getOperand(1));
     break;
   case ISD::UNDEF: {
     MVT::ValueType VT = Op.getValueType();
@@ -844,29 +846,13 @@
   case ISD::CopyToReg:
     Tmp1 = LegalizeOp(Node->getOperand(0));  // Legalize the chain.
 
-    switch (getTypeAction(Node->getOperand(1).getValueType())) {
-    case Legal:
-      // Legalize the incoming value (must be legal).
-      Tmp2 = LegalizeOp(Node->getOperand(1));
-      if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1))
-        Result = DAG.getCopyToReg(Tmp1, Tmp2, cast<RegSDNode>(Node)->getReg());
-      break;
-    case Promote:
-      Tmp2 = PromoteOp(Node->getOperand(1));
-      Result = DAG.getCopyToReg(Tmp1, Tmp2, cast<RegSDNode>(Node)->getReg());
-      break;
-    case Expand:
-      SDOperand Lo, Hi;
-      ExpandOp(Node->getOperand(1), Lo, Hi);
-      unsigned Reg = cast<RegSDNode>(Node)->getReg();
-      Lo = DAG.getCopyToReg(Tmp1, Lo, Reg);
-      Hi = DAG.getCopyToReg(Tmp1, Hi, Reg+1);
-      // Note that the copytoreg nodes are independent of each other.
-      Result = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo, Hi);
-      assert(isTypeLegal(Result.getValueType()) &&
-             "Cannot expand multiple times yet (i64 -> i16)");
-      break;
-    }
+    assert(getTypeAction(Node->getOperand(2).getValueType()) == Legal &&
+           "Register type must be legal!");
+    // Legalize the incoming value (must be legal).
+    Tmp2 = LegalizeOp(Node->getOperand(2));
+    if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(2))
+      Result = DAG.getNode(ISD::CopyToReg, MVT::Other, Tmp1,
+                           Node->getOperand(1), Tmp2);
     break;
 
   case ISD::RET:
@@ -1913,6 +1899,8 @@
   NeedsAnotherIteration = true;
 
   switch (Node->getOpcode()) {
+  case ISD::CopyFromReg:
+    assert(0 && "CopyFromReg must be legal!");
   default:
     std::cerr << "NODE: "; Node->dump(); std::cerr << "\n";
     assert(0 && "Do not know how to promote this operator!");
@@ -1928,12 +1916,6 @@
     Result = DAG.getNode(ISD::FP_EXTEND, NVT, Op);
     assert(isa<ConstantFPSDNode>(Result) && "Didn't constant fold fp_extend?");
     break;
-  case ISD::CopyFromReg:
-    Result = DAG.getCopyFromReg(cast<RegSDNode>(Node)->getReg(), NVT,
-                                Node->getOperand(0));
-    // Remember that we legalized the chain.
-    AddLegalizedOperand(Op.getValue(1), Result.getValue(1));
-    break;
 
   case ISD::SETCC:
     assert(getTypeAction(TLI.getSetCCResultTy()) == Legal &&
@@ -2770,7 +2752,9 @@
   NeedsAnotherIteration = true;
 
   switch (Node->getOpcode()) {
-  default:
+   case ISD::CopyFromReg:
+      assert(0 && "CopyFromReg must be legal!");
+   default:
     std::cerr << "NODE: "; Node->dump(); std::cerr << "\n";
     assert(0 && "Do not know how to expand this operator!");
     abort();
@@ -2785,19 +2769,6 @@
     break;
   }
 
-  case ISD::CopyFromReg: {
-    unsigned Reg = cast<RegSDNode>(Node)->getReg();
-    // Aggregate register values are always in consequtive pairs.
-    Lo = DAG.getCopyFromReg(Reg, NVT, Node->getOperand(0));
-    Hi = DAG.getCopyFromReg(Reg+1, NVT, Lo.getValue(1));
-
-    // Remember that we legalized the chain.
-    AddLegalizedOperand(Op.getValue(1), Hi.getValue(1));
-
-    assert(isTypeLegal(NVT) && "Cannot expand this multiple times yet!");
-    break;
-  }
-
   case ISD::BUILD_PAIR:
     // Legalize both operands.  FIXME: in the future we should handle the case
     // where the two elements are not legal.
diff --git a/lib/CodeGen/SelectionDAG/SelectionDAG.cpp b/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
index 7a790c8..dae19b9 100644
--- a/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
+++ b/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
@@ -250,6 +250,9 @@
   case ISD::VALUETYPE:
     ValueTypeNodes[cast<VTSDNode>(N)->getVT()] = 0;
     break;
+  case ISD::Register:
+    RegNodes[cast<RegisterSDNode>(N)->getReg()] = 0;
+    break;
   case ISD::SRCVALUE: {
     SrcValueSDNode *SVN = cast<SrcValueSDNode>(N);
     ValueNodes.erase(std::make_pair(SVN->getValue(), SVN->getOffset()));
@@ -398,6 +401,20 @@
   return SDOperand(CondCodeNodes[Cond], 0);
 }
 
+SDOperand SelectionDAG::getRegister(unsigned Reg, MVT::ValueType VT) {
+  if (Reg >= RegNodes.size())
+    RegNodes.resize(Reg+1);
+  RegisterSDNode *&Result = RegNodes[Reg];
+  if (Result) {
+    assert(Result->getValueType(0) == VT &&
+           "Inconsistent value types for machine registers");
+  } else {
+    Result = new RegisterSDNode(Reg, VT);
+    AllNodes.push_back(Result);
+  }
+  return SDOperand(Result, 0);
+}
+
 SDOperand SelectionDAG::SimplifySetCC(MVT::ValueType VT, SDOperand N1,
                                       SDOperand N2, ISD::CondCode Cond) {
   // These setcc operations always fold.
@@ -1779,6 +1796,7 @@
   case ISD::GlobalAddress: return "GlobalAddress";
   case ISD::FrameIndex:    return "FrameIndex";
   case ISD::BasicBlock:    return "BasicBlock";
+  case ISD::Register:      return "Register";
   case ISD::ExternalSymbol: return "ExternalSymbol";
   case ISD::ConstantPool:  return "ConstantPoolIndex";
   case ISD::CopyToReg:     return "CopyToReg";
@@ -1939,8 +1957,8 @@
     if (LBB)
       std::cerr << LBB->getName() << " ";
     std::cerr << (const void*)BBDN->getBasicBlock() << ">";
-  } else if (const RegSDNode *C2V = dyn_cast<RegSDNode>(this)) {
-    std::cerr << "<reg #" << C2V->getReg() << ">";
+  } else if (const RegisterSDNode *C2V = dyn_cast<RegisterSDNode>(this)) {
+    std::cerr << " #" << C2V->getReg();
   } else if (const ExternalSymbolSDNode *ES =
              dyn_cast<ExternalSymbolSDNode>(this)) {
     std::cerr << "'" << ES->getSymbol() << "'";
diff --git a/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp b/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
index 512a62d..44553af 100644
--- a/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
+++ b/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
@@ -296,7 +296,27 @@
       FuncInfo.ValueMap.find(V);
     assert(VMI != FuncInfo.ValueMap.end() && "Value not in map!");
 
-    return N = DAG.getCopyFromReg(VMI->second, VT, DAG.getEntryNode());
+    unsigned InReg = VMI->second;
+   
+    // If this type is not legal, make it so now.
+    MVT::ValueType DestVT = TLI.getTypeToTransformTo(VT);
+    
+    N = DAG.getCopyFromReg(DAG.getEntryNode(), InReg, DestVT);
+    if (DestVT < VT) {
+      // Source must be expanded.  This input value is actually coming from the
+      // register pair VMI->second and VMI->second+1.
+      N = DAG.getNode(ISD::BUILD_PAIR, VT, N,
+                      DAG.getCopyFromReg(DAG.getEntryNode(), InReg+1, DestVT));
+    } else {
+      if (DestVT > VT) { // Promotion case
+        if (MVT::isFloatingPoint(VT))
+          N = DAG.getNode(ISD::FP_ROUND, VT, N);
+        else
+          N = DAG.getNode(ISD::TRUNCATE, VT, N);
+      }
+    }
+    
+    return N;
   }
 
   const SDOperand &setValue(const Value *V, SDOperand NewN) {
@@ -957,12 +977,31 @@
 
 SDOperand SelectionDAGISel::
 CopyValueToVirtualRegister(SelectionDAGLowering &SDL, Value *V, unsigned Reg) {
-  SelectionDAG &DAG = SDL.DAG;
   SDOperand Op = SDL.getValue(V);
   assert((Op.getOpcode() != ISD::CopyFromReg ||
-          cast<RegSDNode>(Op)->getReg() != Reg) &&
+          cast<RegisterSDNode>(Op.getOperand(1))->getReg() != Reg) &&
          "Copy from a reg to the same reg!");
-  return DAG.getCopyToReg(SDL.getRoot(), Op, Reg);
+  
+  // If this type is not legal, we must make sure to not create an invalid
+  // register use.
+  MVT::ValueType SrcVT = Op.getValueType();
+  MVT::ValueType DestVT = TLI.getTypeToTransformTo(SrcVT);
+  SelectionDAG &DAG = SDL.DAG;
+  if (SrcVT == DestVT) {
+    return DAG.getCopyToReg(SDL.getRoot(), Reg, Op);
+  } else if (SrcVT < DestVT) {
+    // The src value is promoted to the register.
+    Op = DAG.getNode(ISD::ZERO_EXTEND, DestVT, Op);
+    return DAG.getCopyToReg(SDL.getRoot(), Reg, Op);
+  } else  {
+    // The src value is expanded into multiple registers.
+    SDOperand Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, DestVT,
+                               Op, DAG.getConstant(0, MVT::i32));
+    SDOperand Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, DestVT,
+                               Op, DAG.getConstant(1, MVT::i32));
+    Op = DAG.getCopyToReg(SDL.getRoot(), Reg, Lo);
+    return DAG.getCopyToReg(Op, Reg+1, Hi);
+  }
 }
 
 /// IsOnlyUsedInOneBasicBlock - If the specified argument is only used in a
diff --git a/lib/CodeGen/SelectionDAG/SelectionDAGPrinter.cpp b/lib/CodeGen/SelectionDAG/SelectionDAGPrinter.cpp
index a60acc1..20cec1f 100644
--- a/lib/CodeGen/SelectionDAG/SelectionDAGPrinter.cpp
+++ b/lib/CodeGen/SelectionDAG/SelectionDAGPrinter.cpp
@@ -72,8 +72,8 @@
     if (LBB)
       Op += LBB->getName();
     //Op += " " + (const void*)BBDN->getBasicBlock();
-  } else if (const RegSDNode *C2V = dyn_cast<RegSDNode>(Node)) {
-    Op += " #" + utostr(C2V->getReg());
+  } else if (const RegisterSDNode *R = dyn_cast<RegisterSDNode>(Node)) {
+    Op += " #" + utostr(R->getReg());
   } else if (const ExternalSymbolSDNode *ES =
              dyn_cast<ExternalSymbolSDNode>(Node)) {
     Op += "'" + std::string(ES->getSymbol()) + "'";