llvm_report_error already prints "LLVM ERROR:". So stop reporting errors like "LLVM ERROR: llvm: error:" or "LLVM ERROR: ERROR:".
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77971 91177308-0d34-0410-b5e6-96231b3b80d8
diff --git a/lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp b/lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp
index b08950d..0c410fb 100644
--- a/lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp
+++ b/lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp
@@ -5074,7 +5074,7 @@
Input.ConstraintVT.isInteger()) ||
(OpInfo.ConstraintVT.getSizeInBits() !=
Input.ConstraintVT.getSizeInBits())) {
- llvm_report_error("llvm: error: Unsupported asm: input constraint"
+ llvm_report_error("Unsupported asm: input constraint"
" with a matching output constraint of incompatible"
" type!");
}
@@ -5179,7 +5179,7 @@
// Copy the output from the appropriate register. Find a register that
// we can use.
if (OpInfo.AssignedRegs.Regs.empty()) {
- llvm_report_error("llvm: error: Couldn't allocate output reg for"
+ llvm_report_error("Couldn't allocate output reg for"
" constraint '" + OpInfo.ConstraintCode + "'!");
}
@@ -5233,8 +5233,7 @@
|| (OpFlag & 7) == 6 /* EARLYCLOBBER REGDEF */) {
// Add (OpFlag&0xffff)>>3 registers to MatchedRegs.
if (OpInfo.isIndirect) {
- llvm_report_error("llvm: error: "
- "Don't know how to handle tied indirect "
+ llvm_report_error("Don't know how to handle tied indirect "
"register inputs yet!");
}
RegsForValue MatchedRegs;
@@ -5277,7 +5276,7 @@
TLI.LowerAsmOperandForConstraint(InOperandVal, OpInfo.ConstraintCode[0],
hasMemory, Ops, DAG);
if (Ops.empty()) {
- llvm_report_error("llvm: error: Invalid operand for inline asm"
+ llvm_report_error("Invalid operand for inline asm"
" constraint '" + OpInfo.ConstraintCode + "'!");
}
@@ -5308,7 +5307,7 @@
// Copy the input into the appropriate registers.
if (OpInfo.AssignedRegs.Regs.empty()) {
- llvm_report_error("llvm: error: Couldn't allocate input reg for"
+ llvm_report_error("Couldn't allocate input reg for"
" constraint '"+ OpInfo.ConstraintCode +"'!");
}
diff --git a/lib/ExecutionEngine/Interpreter/Execution.cpp b/lib/ExecutionEngine/Interpreter/Execution.cpp
index b351ba2..8d21d1f 100644
--- a/lib/ExecutionEngine/Interpreter/Execution.cpp
+++ b/lib/ExecutionEngine/Interpreter/Execution.cpp
@@ -644,7 +644,7 @@
}
void Interpreter::visitUnreachableInst(UnreachableInst &I) {
- llvm_report_error("ERROR: Program executed an 'unreachable' instruction!");
+ llvm_report_error("Program executed an 'unreachable' instruction!");
}
void Interpreter::visitBranchInst(BranchInst &I) {
diff --git a/lib/ExecutionEngine/JIT/Intercept.cpp b/lib/ExecutionEngine/JIT/Intercept.cpp
index feb13c6..0dde845 100644
--- a/lib/ExecutionEngine/JIT/Intercept.cpp
+++ b/lib/ExecutionEngine/JIT/Intercept.cpp
@@ -141,7 +141,7 @@
return RP;
if (AbortOnFailure) {
- llvm_report_error("ERROR: Program used external function '"+Name+
+ llvm_report_error("Program used external function '"+Name+
"' which could not be resolved!");
}
return 0;
diff --git a/lib/Target/ARM/ARMCodeEmitter.cpp b/lib/Target/ARM/ARMCodeEmitter.cpp
index ef7c95f..7b497a7 100644
--- a/lib/Target/ARM/ARMCodeEmitter.cpp
+++ b/lib/Target/ARM/ARMCodeEmitter.cpp
@@ -749,7 +749,7 @@
const TargetInstrDesc &TID = MI.getDesc();
if (TID.Opcode == ARM::BFC) {
- llvm_report_error("ERROR: ARMv6t2 JIT is not yet supported.");
+ llvm_report_error("ARMv6t2 JIT is not yet supported.");
}
// Part of binary is determined by TableGn.