diff --git a/lib/CodeGen/PrologEpilogInserter.cpp b/lib/CodeGen/PrologEpilogInserter.cpp
index 882c6a7..9f765d4 100644
--- a/lib/CodeGen/PrologEpilogInserter.cpp
+++ b/lib/CodeGen/PrologEpilogInserter.cpp
@@ -253,7 +253,7 @@
       MBB->addLiveIn(CSI[i].getReg());
 
       // Insert the spill to the stack frame.
-      RegInfo->storeRegToStackSlot(*MBB, I, CSI[i].getReg(),
+      RegInfo->storeRegToStackSlot(*MBB, I, CSI[i].getReg(), true,
                                    CSI[i].getFrameIdx(), CSI[i].getRegClass());
     }
   }
diff --git a/lib/CodeGen/RegAllocBigBlock.cpp b/lib/CodeGen/RegAllocBigBlock.cpp
index 227a238..83c9ceb 100644
--- a/lib/CodeGen/RegAllocBigBlock.cpp
+++ b/lib/CodeGen/RegAllocBigBlock.cpp
@@ -329,7 +329,7 @@
     const TargetRegisterClass *RC = MF->getSSARegMap()->getRegClass(VirtReg);
     int FrameIndex = getStackSpaceFor(VirtReg, RC);
     DOUT << " to stack slot #" << FrameIndex;
-    RegInfo->storeRegToStackSlot(MBB, I, PhysReg, FrameIndex, RC);
+    RegInfo->storeRegToStackSlot(MBB, I, PhysReg, true, FrameIndex, RC);
     ++NumStores;   // Update statistics
   }
 
diff --git a/lib/CodeGen/RegAllocLocal.cpp b/lib/CodeGen/RegAllocLocal.cpp
index a666184..4b4150a 100644
--- a/lib/CodeGen/RegAllocLocal.cpp
+++ b/lib/CodeGen/RegAllocLocal.cpp
@@ -286,7 +286,7 @@
     const TargetRegisterClass *RC = MF->getSSARegMap()->getRegClass(VirtReg);
     int FrameIndex = getStackSpaceFor(VirtReg, RC);
     DOUT << " to stack slot #" << FrameIndex;
-    RegInfo->storeRegToStackSlot(MBB, I, PhysReg, FrameIndex, RC);
+    RegInfo->storeRegToStackSlot(MBB, I, PhysReg, true, FrameIndex, RC);
     ++NumStores;   // Update statistics
   }
 
diff --git a/lib/CodeGen/RegAllocSimple.cpp b/lib/CodeGen/RegAllocSimple.cpp
index f49dd4c..574559a 100644
--- a/lib/CodeGen/RegAllocSimple.cpp
+++ b/lib/CodeGen/RegAllocSimple.cpp
@@ -156,7 +156,7 @@
 
   // Add move instruction(s)
   ++NumStores;
-  RegInfo->storeRegToStackSlot(MBB, I, PhysReg, FrameIdx, RC);
+  RegInfo->storeRegToStackSlot(MBB, I, PhysReg, true, FrameIdx, RC);
 }
 
 
diff --git a/lib/CodeGen/RegisterScavenging.cpp b/lib/CodeGen/RegisterScavenging.cpp
index 1559212..9cb7453 100644
--- a/lib/CodeGen/RegisterScavenging.cpp
+++ b/lib/CodeGen/RegisterScavenging.cpp
@@ -282,7 +282,7 @@
     RegInfo->eliminateFrameIndex(II, SPAdj, this);
   }
 
-  RegInfo->storeRegToStackSlot(*MBB, I, SReg, ScavengingFrameIndex, RC);
+  RegInfo->storeRegToStackSlot(*MBB, I, SReg, true, ScavengingFrameIndex, RC);
   MachineBasicBlock::iterator II = prior(I);
   RegInfo->eliminateFrameIndex(II, SPAdj, this);
   ScavengedReg = SReg;
diff --git a/lib/CodeGen/VirtRegMap.cpp b/lib/CodeGen/VirtRegMap.cpp
index 58fc40b..6c04439 100644
--- a/lib/CodeGen/VirtRegMap.cpp
+++ b/lib/CodeGen/VirtRegMap.cpp
@@ -208,7 +208,8 @@
               }
 
               if (MO.isDef()) {
-                MRI.storeRegToStackSlot(MBB, next(MII), PhysReg, StackSlot, RC);
+                MRI.storeRegToStackSlot(MBB, next(MII), PhysReg, true,
+                                        StackSlot, RC);
                 ++NumStores;
               }
             }
@@ -861,7 +862,7 @@
                                   BitVector &RegKills,
                                   std::vector<MachineOperand*> &KillOps,
                                   VirtRegMap &VRM) {
-  MRI->storeRegToStackSlot(MBB, next(MII), PhysReg, StackSlot, RC);
+  MRI->storeRegToStackSlot(MBB, next(MII), PhysReg, true, StackSlot, RC);
   DOUT << "Store:\t" << *next(MII);
 
   // If there is a dead store to this stack slot, nuke it now.
@@ -984,9 +985,10 @@
         const TargetRegisterClass *RC = RegMap->getRegClass(VirtReg);
         unsigned Phys = VRM.getPhys(VirtReg);
         int StackSlot = VRM.getStackSlot(VirtReg);
-        MRI->storeRegToStackSlot(MBB, next(MII), Phys, StackSlot, RC);
-        DOUT << "Store:\t" << *next(MII);
-        VRM.virtFolded(VirtReg, next(MII), VirtRegMap::isMod);
+        MRI->storeRegToStackSlot(MBB, next(MII), Phys, false, StackSlot, RC);
+        MachineInstr *StoreMI = next(MII);
+        DOUT << "Store:\t" << StoreMI;
+        VRM.virtFolded(VirtReg, StoreMI, VirtRegMap::isMod);
       }
       NextMII = next(MII);
     }
@@ -1011,12 +1013,6 @@
       assert(MRegisterInfo::isVirtualRegister(VirtReg) &&
              "Not a virtual or a physical register?");
 
-      // Assumes this is the last use of a split interval. IsKill will be unset
-      // if reg is use later unless it's a two-address operand.
-      if (MO.isUse() && VRM.getPreSplitReg(VirtReg) &&
-          TID->getOperandConstraint(i, TOI::TIED_TO) == -1)
-        MI.getOperand(i).setIsKill();
-
       unsigned SubIdx = MO.getSubReg();
       if (VRM.isAssignedReg(VirtReg)) {
         // This virtual register was assigned a physreg!