ARM has to provide its own TargetLowering::findRepresentativeClass because its scalar floating point registers alias its vector registers.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108761 91177308-0d34-0410-b5e6-96231b3b80d8
diff --git a/lib/Target/ARM/ARMISelLowering.cpp b/lib/Target/ARM/ARMISelLowering.cpp
index 9b6db1d..9102664 100644
--- a/lib/Target/ARM/ARMISelLowering.cpp
+++ b/lib/Target/ARM/ARMISelLowering.cpp
@@ -550,6 +550,22 @@
benefitFromCodePlacementOpt = true;
}
+const TargetRegisterClass *
+ARMTargetLowering::findRepresentativeClass(const TargetRegisterClass *RC) const{
+ switch (RC->getID()) {
+ default:
+ return RC;
+ case ARM::tGPRRegClassID:
+ case ARM::GPRRegClassID:
+ return ARM::GPRRegisterClass;
+ case ARM::SPRRegClassID:
+ case ARM::DPRRegClassID:
+ return ARM::DPRRegisterClass;
+ case ARM::QPRRegClassID:
+ return ARM::QPRRegisterClass;
+ }
+}
+
const char *ARMTargetLowering::getTargetNodeName(unsigned Opcode) const {
switch (Opcode) {
default: return 0;