Switch the MachineOperand accessors back to the short names like
isReg, etc., from isRegister, etc.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@57006 91177308-0d34-0410-b5e6-96231b3b80d8
diff --git a/lib/Target/ARM/ARMCodeEmitter.cpp b/lib/Target/ARM/ARMCodeEmitter.cpp
index ceb6fc5..1086242 100644
--- a/lib/Target/ARM/ARMCodeEmitter.cpp
+++ b/lib/Target/ARM/ARMCodeEmitter.cpp
@@ -181,19 +181,19 @@
/// operand requires relocation, record the relocation and return zero.
unsigned ARMCodeEmitter::getMachineOpValue(const MachineInstr &MI,
const MachineOperand &MO) {
- if (MO.isRegister())
+ if (MO.isReg())
return ARMRegisterInfo::getRegisterNumbering(MO.getReg());
- else if (MO.isImmediate())
+ else if (MO.isImm())
return static_cast<unsigned>(MO.getImm());
- else if (MO.isGlobalAddress())
+ else if (MO.isGlobal())
emitGlobalAddress(MO.getGlobal(), ARM::reloc_arm_branch, false);
- else if (MO.isExternalSymbol())
+ else if (MO.isSymbol())
emitExternalSymbolAddress(MO.getSymbolName(), ARM::reloc_arm_relative);
- else if (MO.isConstantPoolIndex())
+ else if (MO.isCPI())
emitConstPoolAddress(MO.getIndex(), ARM::reloc_arm_relative);
- else if (MO.isJumpTableIndex())
+ else if (MO.isJTI())
emitJumpTableAddress(MO.getIndex(), ARM::reloc_arm_relative);
- else if (MO.isMachineBasicBlock())
+ else if (MO.isMBB())
emitMachineBasicBlock(MO.getMBB());
else {
cerr << "ERROR: Unknown type of MachineOperand: " << MO << "\n";
@@ -351,7 +351,7 @@
const TargetInstrDesc &TID) const {
for (unsigned i = MI.getNumOperands(), e = TID.getNumOperands(); i != e; --i){
const MachineOperand &MO = MI.getOperand(i-1);
- if (MO.isRegister() && MO.isDef() && MO.getReg() == ARM::CPSR)
+ if (MO.isReg() && MO.isDef() && MO.getReg() == ARM::CPSR)
return 1 << ARMII::S_BitShift;
}
return 0;
@@ -414,7 +414,7 @@
return Binary | getMachineSoRegOpValue(MI, TID, OpIdx);
const MachineOperand &MO = MI.getOperand(OpIdx);
- if (MO.isRegister())
+ if (MO.isReg())
// Encode register Rm.
return Binary | getMachineOpValue(MI, NumDefs + 1);
@@ -538,7 +538,7 @@
// Set registers
for (unsigned i = 4, e = MI.getNumOperands(); i != e; ++i) {
const MachineOperand &MO = MI.getOperand(i);
- if (MO.isRegister() && MO.isImplicit())
+ if (MO.isReg() && MO.isImplicit())
continue;
unsigned RegNum = ARMRegisterInfo::getRegisterNumbering(MO.getReg());
assert(TargetRegisterInfo::isPhysicalRegister(MO.getReg()) &&
diff --git a/lib/Target/ARM/ARMConstantIslandPass.cpp b/lib/Target/ARM/ARMConstantIslandPass.cpp
index 3ddffde..5d13847 100644
--- a/lib/Target/ARM/ARMConstantIslandPass.cpp
+++ b/lib/Target/ARM/ARMConstantIslandPass.cpp
@@ -416,7 +416,7 @@
// Scan the instructions for constant pool operands.
for (unsigned op = 0, e = I->getNumOperands(); op != e; ++op)
- if (I->getOperand(op).isConstantPoolIndex()) {
+ if (I->getOperand(op).isCPI()) {
// We found one. The addressing mode tells us the max displacement
// from the PC that this instruction permits.
@@ -818,7 +818,7 @@
U.CPEMI = CPEs[i].CPEMI;
// Change the CPI in the instruction operand to refer to the clone.
for (unsigned j = 0, e = UserMI->getNumOperands(); j != e; ++j)
- if (UserMI->getOperand(j).isConstantPoolIndex()) {
+ if (UserMI->getOperand(j).isCPI()) {
UserMI->getOperand(j).setIndex(CPEs[i].CPI);
break;
}
@@ -1058,7 +1058,7 @@
// Finally, change the CPI in the instruction operand to be ID.
for (unsigned i = 0, e = UserMI->getNumOperands(); i != e; ++i)
- if (UserMI->getOperand(i).isConstantPoolIndex()) {
+ if (UserMI->getOperand(i).isCPI()) {
UserMI->getOperand(i).setIndex(ID);
break;
}
diff --git a/lib/Target/ARM/ARMInstrInfo.cpp b/lib/Target/ARM/ARMInstrInfo.cpp
index 839ee6a..e1f44bd 100644
--- a/lib/Target/ARM/ARMInstrInfo.cpp
+++ b/lib/Target/ARM/ARMInstrInfo.cpp
@@ -64,8 +64,8 @@
case ARM::MOVr:
case ARM::tMOVr:
assert(MI.getDesc().getNumOperands() >= 2 &&
- MI.getOperand(0).isRegister() &&
- MI.getOperand(1).isRegister() &&
+ MI.getOperand(0).isReg() &&
+ MI.getOperand(1).isReg() &&
"Invalid ARM MOV instruction");
SrcReg = MI.getOperand(1).getReg();
DstReg = MI.getOperand(0).getReg();
@@ -77,9 +77,9 @@
switch (MI->getOpcode()) {
default: break;
case ARM::LDR:
- if (MI->getOperand(1).isFrameIndex() &&
- MI->getOperand(2).isRegister() &&
- MI->getOperand(3).isImmediate() &&
+ if (MI->getOperand(1).isFI() &&
+ MI->getOperand(2).isReg() &&
+ MI->getOperand(3).isImm() &&
MI->getOperand(2).getReg() == 0 &&
MI->getOperand(3).getImm() == 0) {
FrameIndex = MI->getOperand(1).getIndex();
@@ -88,16 +88,16 @@
break;
case ARM::FLDD:
case ARM::FLDS:
- if (MI->getOperand(1).isFrameIndex() &&
- MI->getOperand(2).isImmediate() &&
+ if (MI->getOperand(1).isFI() &&
+ MI->getOperand(2).isImm() &&
MI->getOperand(2).getImm() == 0) {
FrameIndex = MI->getOperand(1).getIndex();
return MI->getOperand(0).getReg();
}
break;
case ARM::tRestore:
- if (MI->getOperand(1).isFrameIndex() &&
- MI->getOperand(2).isImmediate() &&
+ if (MI->getOperand(1).isFI() &&
+ MI->getOperand(2).isImm() &&
MI->getOperand(2).getImm() == 0) {
FrameIndex = MI->getOperand(1).getIndex();
return MI->getOperand(0).getReg();
@@ -111,9 +111,9 @@
switch (MI->getOpcode()) {
default: break;
case ARM::STR:
- if (MI->getOperand(1).isFrameIndex() &&
- MI->getOperand(2).isRegister() &&
- MI->getOperand(3).isImmediate() &&
+ if (MI->getOperand(1).isFI() &&
+ MI->getOperand(2).isReg() &&
+ MI->getOperand(3).isImm() &&
MI->getOperand(2).getReg() == 0 &&
MI->getOperand(3).getImm() == 0) {
FrameIndex = MI->getOperand(1).getIndex();
@@ -122,16 +122,16 @@
break;
case ARM::FSTD:
case ARM::FSTS:
- if (MI->getOperand(1).isFrameIndex() &&
- MI->getOperand(2).isImmediate() &&
+ if (MI->getOperand(1).isFI() &&
+ MI->getOperand(2).isImm() &&
MI->getOperand(2).getImm() == 0) {
FrameIndex = MI->getOperand(1).getIndex();
return MI->getOperand(0).getReg();
}
break;
case ARM::tSpill:
- if (MI->getOperand(1).isFrameIndex() &&
- MI->getOperand(2).isImmediate() &&
+ if (MI->getOperand(1).isFI() &&
+ MI->getOperand(2).isImm() &&
MI->getOperand(2).getImm() == 0) {
FrameIndex = MI->getOperand(1).getIndex();
return MI->getOperand(0).getReg();
@@ -298,7 +298,7 @@
// Transfer LiveVariables states, kill / dead info.
for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
MachineOperand &MO = MI->getOperand(i);
- if (MO.isRegister() && MO.getReg() &&
+ if (MO.isReg() && MO.getReg() &&
TargetRegisterInfo::isVirtualRegister(MO.getReg())) {
unsigned Reg = MO.getReg();
@@ -491,11 +491,11 @@
static const MachineInstrBuilder &ARMInstrAddOperand(MachineInstrBuilder &MIB,
MachineOperand &MO) {
- if (MO.isRegister())
+ if (MO.isReg())
MIB = MIB.addReg(MO.getReg(), MO.isDef(), MO.isImplicit());
- else if (MO.isImmediate())
+ else if (MO.isImm())
MIB = MIB.addImm(MO.getImm());
- else if (MO.isFrameIndex())
+ else if (MO.isFI())
MIB = MIB.addFrameIndex(MO.getIndex());
else
assert(0 && "Unknown operand for ARMInstrAddOperand!");
@@ -538,7 +538,7 @@
if (RC == ARM::GPRRegisterClass) {
ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
if (AFI->isThumbFunction()) {
- Opc = Addr[0].isFrameIndex() ? ARM::tSpill : ARM::tSTR;
+ Opc = Addr[0].isFI() ? ARM::tSpill : ARM::tSTR;
MachineInstrBuilder MIB =
BuildMI(MF, get(Opc)).addReg(SrcReg, false, false, isKill);
for (unsigned i = 0, e = Addr.size(); i != e; ++i)
@@ -594,7 +594,7 @@
if (RC == ARM::GPRRegisterClass) {
ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
if (AFI->isThumbFunction()) {
- Opc = Addr[0].isFrameIndex() ? ARM::tRestore : ARM::tLDR;
+ Opc = Addr[0].isFI() ? ARM::tRestore : ARM::tLDR;
MachineInstrBuilder MIB = BuildMI(MF, get(Opc), DestReg);
for (unsigned i = 0, e = Addr.size(); i != e; ++i)
MIB = ARMInstrAddOperand(MIB, Addr[i]);
@@ -868,7 +868,7 @@
bool Found = false;
for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
const MachineOperand &MO = MI->getOperand(i);
- if (MO.isRegister() && MO.getReg() == ARM::CPSR) {
+ if (MO.isReg() && MO.getReg() == ARM::CPSR) {
Pred.push_back(MO);
Found = true;
}
diff --git a/lib/Target/ARM/ARMLoadStoreOptimizer.cpp b/lib/Target/ARM/ARMLoadStoreOptimizer.cpp
index 8bd4caa..27fec1f 100644
--- a/lib/Target/ARM/ARMLoadStoreOptimizer.cpp
+++ b/lib/Target/ARM/ARMLoadStoreOptimizer.cpp
@@ -544,13 +544,13 @@
default: break;
case ARM::LDR:
case ARM::STR:
- return MI->getOperand(1).isRegister() && MI->getOperand(2).getReg() == 0;
+ return MI->getOperand(1).isReg() && MI->getOperand(2).getReg() == 0;
case ARM::FLDS:
case ARM::FSTS:
- return MI->getOperand(1).isRegister();
+ return MI->getOperand(1).isReg();
case ARM::FLDD:
case ARM::FSTD:
- return MI->getOperand(1).isRegister();
+ return MI->getOperand(1).isReg();
}
return false;
}
diff --git a/lib/Target/ARM/ARMRegisterInfo.cpp b/lib/Target/ARM/ARMRegisterInfo.cpp
index 3a0a57d..2091899 100644
--- a/lib/Target/ARM/ARMRegisterInfo.cpp
+++ b/lib/Target/ARM/ARMRegisterInfo.cpp
@@ -540,7 +540,7 @@
ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
bool isThumb = AFI->isThumbFunction();
- while (!MI.getOperand(i).isFrameIndex()) {
+ while (!MI.getOperand(i).isFI()) {
++i;
assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!");
}
@@ -1020,7 +1020,7 @@
for (MachineFunction::iterator BB = MF.begin(),E = MF.end();BB != E; ++BB)
for (MachineBasicBlock::iterator I= BB->begin(); I != BB->end(); ++I) {
for (unsigned i = 0, e = I->getNumOperands(); i != e; ++i)
- if (I->getOperand(i).isFrameIndex()) {
+ if (I->getOperand(i).isFI()) {
unsigned Opcode = I->getOpcode();
const TargetInstrDesc &Desc = TII.get(Opcode);
unsigned AddrMode = (Desc.TSFlags & ARMII::AddrModeMask);
@@ -1086,7 +1086,7 @@
int Opc, unsigned Area,
const ARMSubtarget &STI) {
while (MBBI != MBB.end() &&
- MBBI->getOpcode() == Opc && MBBI->getOperand(1).isFrameIndex()) {
+ MBBI->getOpcode() == Opc && MBBI->getOperand(1).isFI()) {
if (Area != 0) {
bool Done = false;
unsigned Category = 0;
@@ -1250,7 +1250,7 @@
return ((MI->getOpcode() == ARM::FLDD ||
MI->getOpcode() == ARM::LDR ||
MI->getOpcode() == ARM::tRestore) &&
- MI->getOperand(1).isFrameIndex() &&
+ MI->getOperand(1).isFI() &&
isCalleeSavedRegister(MI->getOperand(0).getReg(), CSRegs));
}
diff --git a/lib/Target/ARM/AsmPrinter/ARMAsmPrinter.cpp b/lib/Target/ARM/AsmPrinter/ARMAsmPrinter.cpp
index 8789b82..62bf87b 100644
--- a/lib/Target/ARM/AsmPrinter/ARMAsmPrinter.cpp
+++ b/lib/Target/ARM/AsmPrinter/ARMAsmPrinter.cpp
@@ -359,7 +359,7 @@
/// immediate in bits 0-7.
void ARMAsmPrinter::printSOImmOperand(const MachineInstr *MI, int OpNum) {
const MachineOperand &MO = MI->getOperand(OpNum);
- assert(MO.isImmediate() && "Not a valid so_imm value!");
+ assert(MO.isImm() && "Not a valid so_imm value!");
printSOImm(O, MO.getImm(), TAI);
}
@@ -367,7 +367,7 @@
/// followed by a or to materialize.
void ARMAsmPrinter::printSOImm2PartOperand(const MachineInstr *MI, int OpNum) {
const MachineOperand &MO = MI->getOperand(OpNum);
- assert(MO.isImmediate() && "Not a valid so_imm value!");
+ assert(MO.isImm() && "Not a valid so_imm value!");
unsigned V1 = ARM_AM::getSOImmTwoPartFirst(MO.getImm());
unsigned V2 = ARM_AM::getSOImmTwoPartSecond(MO.getImm());
printSOImm(O, ARM_AM::getSOImmVal(V1), TAI);
@@ -413,7 +413,7 @@
const MachineOperand &MO2 = MI->getOperand(Op+1);
const MachineOperand &MO3 = MI->getOperand(Op+2);
- if (!MO1.isRegister()) { // FIXME: This is for CP entries, but isn't right.
+ if (!MO1.isReg()) { // FIXME: This is for CP entries, but isn't right.
printOperand(MI, Op);
return;
}
@@ -526,7 +526,7 @@
const MachineOperand &MO1 = MI->getOperand(Op);
const MachineOperand &MO2 = MI->getOperand(Op+1);
- if (!MO1.isRegister()) { // FIXME: This is for CP entries, but isn't right.
+ if (!MO1.isReg()) { // FIXME: This is for CP entries, but isn't right.
printOperand(MI, Op);
return;
}
@@ -587,7 +587,7 @@
const MachineOperand &MO2 = MI->getOperand(Op+1);
const MachineOperand &MO3 = MI->getOperand(Op+2);
- if (!MO1.isRegister()) { // FIXME: This is for CP entries, but isn't right.
+ if (!MO1.isReg()) { // FIXME: This is for CP entries, but isn't right.
printOperand(MI, Op);
return;
}
@@ -749,9 +749,9 @@
// Fallthrough
case 'H': // Write second word of DI / DF reference.
// Verify that this operand has two consecutive registers.
- if (!MI->getOperand(OpNo).isRegister() ||
+ if (!MI->getOperand(OpNo).isReg() ||
OpNo+1 == MI->getNumOperands() ||
- !MI->getOperand(OpNo+1).isRegister())
+ !MI->getOperand(OpNo+1).isReg())
return true;
++OpNo; // Return the high-part.
}