diff --git a/lib/Target/ARM/ARMISelDAGToDAG.cpp b/lib/Target/ARM/ARMISelDAGToDAG.cpp
index 0a48978..7cf7dd3 100644
--- a/lib/Target/ARM/ARMISelDAGToDAG.cpp
+++ b/lib/Target/ARM/ARMISelDAGToDAG.cpp
@@ -31,7 +31,7 @@
 namespace ARMISD {
   enum {
     FIRST_NUMBER = ISD::BUILTIN_OP_END+ARM::INSTRUCTION_LIST_END,
-    RET_FLAG,
+    RET_FLAG
   };
 }
 
diff --git a/lib/Target/Alpha/AlphaISelLowering.h b/lib/Target/Alpha/AlphaISelLowering.h
index 569fa74..d6886fc 100644
--- a/lib/Target/Alpha/AlphaISelLowering.h
+++ b/lib/Target/Alpha/AlphaISelLowering.h
@@ -42,7 +42,7 @@
       CALL,
 
       /// DIVCALL - used for special library calls for div and rem
-      DivCall,
+      DivCall
 
     };
   }
diff --git a/lib/Target/Alpha/AlphaRelocations.h b/lib/Target/Alpha/AlphaRelocations.h
index 59b9765..c532f21 100644
--- a/lib/Target/Alpha/AlphaRelocations.h
+++ b/lib/Target/Alpha/AlphaRelocations.h
@@ -23,7 +23,7 @@
       reloc_gprellow,
       reloc_gprelhigh,
       reloc_gpdist,
-      reloc_bsr,
+      reloc_bsr
     };
   }
 }
diff --git a/lib/Target/PowerPC/PPCISelLowering.cpp b/lib/Target/PowerPC/PPCISelLowering.cpp
index 1e6c1e5..850b412 100644
--- a/lib/Target/PowerPC/PPCISelLowering.cpp
+++ b/lib/Target/PowerPC/PPCISelLowering.cpp
@@ -1748,7 +1748,7 @@
     OP_VSPLTISW3,
     OP_VSLDOI4,
     OP_VSLDOI8,
-    OP_VSLDOI12,
+    OP_VSLDOI12
   };
   
   if (OpNum == OP_COPY) {
diff --git a/lib/Target/PowerPC/PPCInstrInfo.h b/lib/Target/PowerPC/PPCInstrInfo.h
index 857d42b..25551fb 100644
--- a/lib/Target/PowerPC/PPCInstrInfo.h
+++ b/lib/Target/PowerPC/PPCInstrInfo.h
@@ -44,7 +44,7 @@
   /// PPC970_Mask/Shift - This is a bitmask that selects the pipeline type that
   /// an instruction is issued to.
   PPC970_Shift = 3,
-  PPC970_Mask = 0x07 << PPC970_Shift,
+  PPC970_Mask = 0x07 << PPC970_Shift
 };
 enum PPC970_Unit {
   /// These are the various PPC970 execution unit pipelines.  Each instruction
@@ -56,7 +56,7 @@
   PPC970_CRU    = 4 << PPC970_Shift,   // Control Register Unit
   PPC970_VALU   = 5 << PPC970_Shift,   // Vector ALU
   PPC970_VPERM  = 6 << PPC970_Shift,   // Vector Permute Unit
-  PPC970_BRU    = 7 << PPC970_Shift,   // Branch Unit
+  PPC970_BRU    = 7 << PPC970_Shift    // Branch Unit
 };
 }
   
diff --git a/lib/Target/PowerPC/PPCJITInfo.cpp b/lib/Target/PowerPC/PPCJITInfo.cpp
index a6d630e..6ee10d7 100644
--- a/lib/Target/PowerPC/PPCJITInfo.cpp
+++ b/lib/Target/PowerPC/PPCJITInfo.cpp
@@ -165,7 +165,7 @@
 void *PPCJITInfo::emitFunctionStub(void *Fn, MachineCodeEmitter &MCE) {
   // If this is just a call to an external function, emit a branch instead of a
   // call.  The code is the same except for one bit of the last instruction.
-  if (Fn != PPC32CompilationCallback) {
+  if (Fn != (void*)PPC32CompilationCallback) {
     MCE.startFunctionStub(4*4);
     void *Addr = (void*)(intptr_t)MCE.getCurrentPCValue();
     MCE.emitWordBE(0);
diff --git a/lib/Target/PowerPC/PPCRelocations.h b/lib/Target/PowerPC/PPCRelocations.h
index 77c3519..20d747b 100644
--- a/lib/Target/PowerPC/PPCRelocations.h
+++ b/lib/Target/PowerPC/PPCRelocations.h
@@ -50,7 +50,7 @@
       // relocated to point to a POINTER to the indicated global.  The low-16
       // bits of the instruction are rewritten with the low 16-bits of the
       // address of the pointer.
-      reloc_absolute_ptr_low,
+      reloc_absolute_ptr_low
     };
   }
 }
diff --git a/lib/Target/Sparc/Sparc.h b/lib/Target/Sparc/Sparc.h
index 084bfe3..c2ae18d 100644
--- a/lib/Target/Sparc/Sparc.h
+++ b/lib/Target/Sparc/Sparc.h
@@ -75,7 +75,7 @@
       FCC_UGE = 12+16,  // Unordered or Greater or Equal
       FCC_LE  = 13+16,  // Less or Equal
       FCC_ULE = 14+16,  // Unordered or Less or Equal
-      FCC_O   = 15+16,  // Ordered
+      FCC_O   = 15+16   // Ordered
     };
   }
   
diff --git a/lib/Target/Sparc/SparcISelDAGToDAG.cpp b/lib/Target/Sparc/SparcISelDAGToDAG.cpp
index 123b86a..25f6e23 100644
--- a/lib/Target/Sparc/SparcISelDAGToDAG.cpp
+++ b/lib/Target/Sparc/SparcISelDAGToDAG.cpp
@@ -48,7 +48,7 @@
     ITOF,        // Int to FP within a FP register.
 
     CALL,        // A call instruction.
-    RET_FLAG,    // Return with a flag operand.
+    RET_FLAG     // Return with a flag operand.
   };
 }
 
diff --git a/lib/Target/Sparc/SparcInstrInfo.h b/lib/Target/Sparc/SparcInstrInfo.h
index 3dd8b8e..166793e 100644
--- a/lib/Target/Sparc/SparcInstrInfo.h
+++ b/lib/Target/Sparc/SparcInstrInfo.h
@@ -29,7 +29,7 @@
     Store = (1<<2),
     DelaySlot = (1<<3)
   };
-};
+}
 
 class SparcInstrInfo : public TargetInstrInfo {
   const SparcRegisterInfo RI;
diff --git a/lib/Target/Sparc/SparcSubtarget.cpp b/lib/Target/Sparc/SparcSubtarget.cpp
index beda79d..9940fcf 100644
--- a/lib/Target/Sparc/SparcSubtarget.cpp
+++ b/lib/Target/Sparc/SparcSubtarget.cpp
@@ -40,4 +40,4 @@
   // Unless explicitly enabled, disable the V9 instructions.
   if (!EnableV9)
     IsV9 = false;
-};
+}
diff --git a/lib/Target/TargetMachine.cpp b/lib/Target/TargetMachine.cpp
index bf70d12..c9e92fa 100644
--- a/lib/Target/TargetMachine.cpp
+++ b/lib/Target/TargetMachine.cpp
@@ -28,7 +28,7 @@
   bool UnsafeFPMath;
   bool FiniteOnlyFPMathOption;
   Reloc::Model RelocationModel;
-};
+}
 namespace {
   cl::opt<bool, true> PrintCode("print-machineinstrs",
     cl::desc("Print generated machine code"),
@@ -70,7 +70,7 @@
       clEnumValN(Reloc::DynamicNoPIC, "dynamic-no-pic",
                  "Relocatable external references, non-relocatable code"),
       clEnumValEnd));
-};
+}
 
 //---------------------------------------------------------------------------
 // TargetMachine Class
diff --git a/lib/Target/X86/X86ISelDAGToDAG.cpp b/lib/Target/X86/X86ISelDAGToDAG.cpp
index 50c42ec..b53748a 100644
--- a/lib/Target/X86/X86ISelDAGToDAG.cpp
+++ b/lib/Target/X86/X86ISelDAGToDAG.cpp
@@ -47,7 +47,7 @@
   struct X86ISelAddressMode {
     enum {
       RegBase,
-      FrameIndexBase,
+      FrameIndexBase
     } BaseType;
 
     struct {            // This is really a union, discriminated by BaseType!
diff --git a/lib/Target/X86/X86ISelLowering.h b/lib/Target/X86/X86ISelLowering.h
index 9269daf..38aa227 100644
--- a/lib/Target/X86/X86ISelLowering.h
+++ b/lib/Target/X86/X86ISelLowering.h
@@ -156,7 +156,7 @@
 
       /// PINSRW - Insert the lower 16-bits of a 32-bit value to a vector,
       /// corresponds to X86::PINSRW.
-      PINSRW,
+      PINSRW
     };
 
     // X86 specific condition code. These correspond to X86_*_COND in
diff --git a/lib/Target/X86/X86InstrBuilder.h b/lib/Target/X86/X86InstrBuilder.h
index f3e1c28..c0fa58d 100644
--- a/lib/Target/X86/X86InstrBuilder.h
+++ b/lib/Target/X86/X86InstrBuilder.h
@@ -35,7 +35,7 @@
 struct X86AddressMode {
   enum {
     RegBase,
-    FrameIndexBase,
+    FrameIndexBase
   } BaseType;
 
   union {
diff --git a/lib/Target/X86/X86InstrInfo.h b/lib/Target/X86/X86InstrInfo.h
index d6dfae1..b49c351 100644
--- a/lib/Target/X86/X86InstrInfo.h
+++ b/lib/Target/X86/X86InstrInfo.h
@@ -162,7 +162,7 @@
     SpecialFP  = 7 << FPTypeShift,
 
     OpcodeShift   = 16,
-    OpcodeMask    = 0xFF << OpcodeShift,
+    OpcodeMask    = 0xFF << OpcodeShift
     // Bits 25 -> 31 are unused
   };
 }
diff --git a/lib/Target/X86/X86JITInfo.cpp b/lib/Target/X86/X86JITInfo.cpp
index 3d12221..6f83651 100644
--- a/lib/Target/X86/X86JITInfo.cpp
+++ b/lib/Target/X86/X86JITInfo.cpp
@@ -167,7 +167,7 @@
 }
 
 void *X86JITInfo::emitFunctionStub(void *Fn, MachineCodeEmitter &MCE) {
-  if (Fn != X86CompilationCallback) {
+  if (Fn != (void*)X86CompilationCallback) {
     MCE.startFunctionStub(5);
     MCE.emitByte(0xE9);
     MCE.emitWordLE((intptr_t)Fn-MCE.getCurrentPCValue()-4);
diff --git a/lib/Target/X86/X86Relocations.h b/lib/Target/X86/X86Relocations.h
index 7a5f1a6..bc1efabc 100644
--- a/lib/Target/X86/X86Relocations.h
+++ b/lib/Target/X86/X86Relocations.h
@@ -25,7 +25,7 @@
 
       // reloc_absolute_word - Absolute relocation, just add the relocated value
       // to the value already in memory.
-      reloc_absolute_word = 1,
+      reloc_absolute_word = 1
     };
   }
 }