commit d76773a22169fae235be98df7034bc2544492333
author Cameron Zwarich <zwarich@apple.com> Thu May 19 03:11:06 2011 +0000
committer Cameron Zwarich <zwarich@apple.com> Thu May 19 03:11:06 2011 +0000
tree 436181dbc591440d35c1af72ae1c4fe93e0724f9
parent 0113e4e3f242fef41e6c733d1945f9950276cc9c

Make CodeGen/PowerPC/2007-09-11-RegCoalescerAssert.ll pass with the verifier.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131627 91177308-0d34-0410-b5e6-96231b3b80d8

lib/Target/PowerPC/PPCISelLowering.cpp

diff --git a/lib/Target/PowerPC/PPCISelLowering.cpp b/lib/Target/PowerPC/PPCISelLowering.cpp
index 625c963..a5a3b01 100644
--- a/lib/Target/PowerPC/PPCISelLowering.cpp
+++ b/lib/Target/PowerPC/PPCISelLowering.cpp
@@ -1010,7 +1010,8 @@
       short Imm;
       if (isIntS16Immediate(CN, Imm)) {
         Disp = DAG.getTargetConstant((unsigned short)Imm >> 2, getPointerTy());
-        Base = DAG.getRegister(PPC::R0, CN->getValueType(0));
+        Base = DAG.getRegister(PPCSubTarget.isPPC64() ? PPC::X0 : PPC::R0,
+                               CN->getValueType(0));
         return true;
       }