misched prep: Comment the ScheduleDAGInstrs interface.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152259 91177308-0d34-0410-b5e6-96231b3b80d8
diff --git a/lib/CodeGen/ScheduleDAGInstrs.cpp b/lib/CodeGen/ScheduleDAGInstrs.cpp
index c4addee..d2351a3 100644
--- a/lib/CodeGen/ScheduleDAGInstrs.cpp
+++ b/lib/CodeGen/ScheduleDAGInstrs.cpp
@@ -38,8 +38,9 @@
bool IsPostRAFlag,
LiveIntervals *lis)
: ScheduleDAG(mf), MLI(mli), MDT(mdt), MFI(mf.getFrameInfo()),
- InstrItins(mf.getTarget().getInstrItineraryData()), IsPostRA(IsPostRAFlag),
- LIS(lis), UnitLatencies(false), LoopRegs(MLI, MDT), FirstDbgValue(0) {
+ InstrItins(mf.getTarget().getInstrItineraryData()), LIS(lis),
+ IsPostRA(IsPostRAFlag), UnitLatencies(false), LoopRegs(MLI, MDT),
+ FirstDbgValue(0) {
assert((IsPostRA || LIS) && "PreRA scheduling requires LiveIntervals");
DbgValues.clear();
assert(!(IsPostRA && MRI.getNumVirtRegs()) &&
diff --git a/lib/CodeGen/ScheduleDAGInstrs.h b/lib/CodeGen/ScheduleDAGInstrs.h
index 714de4e..27fb11c 100644
--- a/lib/CodeGen/ScheduleDAGInstrs.h
+++ b/lib/CodeGen/ScheduleDAGInstrs.h
@@ -171,16 +171,20 @@
const MachineFrameInfo *MFI;
const InstrItineraryData *InstrItins;
- /// isPostRA flag indicates vregs cannot be present.
- bool IsPostRA;
-
/// Live Intervals provides reaching defs in preRA scheduling.
LiveIntervals *LIS;
- /// State specific to the current scheduling region.
- ///
+ /// isPostRA flag indicates vregs cannot be present.
+ bool IsPostRA;
- // The block in which to insert instructions
+ /// UnitLatencies (misnamed) flag avoids computing def-use latencies, using
+ /// the def-side latency only.
+ bool UnitLatencies;
+
+ /// State specific to the current scheduling region.
+ /// ------------------------------------------------
+
+ /// The block in which to insert instructions
MachineBasicBlock *BB;
/// The beginning of the range to be scheduled.
@@ -196,9 +200,8 @@
/// scheduling region is mapped to an SUnit.
DenseMap<MachineInstr*, SUnit*> MISUnitMap;
- /// UnitLatencies (misnamed) flag avoids computing def-use latencies, using
- /// the def-side latency only.
- bool UnitLatencies;
+ /// State internal to DAG building.
+ /// -------------------------------
/// Defs, Uses - Remember where defs and uses of each register are as we
/// iterate upward through the instructions. This is allocated here instead
@@ -220,6 +223,8 @@
LoopDependencies LoopRegs;
/// DbgValues - Remember instruction that preceeds DBG_VALUE.
+ /// These are generated by buildSchedGraph but persist so they can be
+ /// referenced when emitting the final schedule.
typedef std::vector<std::pair<MachineInstr *, MachineInstr *> >
DbgValueVector;
DbgValueVector DbgValues;