Enable predication of NEON instructions in Thumb2 mode.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@89748 91177308-0d34-0410-b5e6-96231b3b80d8
diff --git a/lib/Target/ARM/ARMBaseInstrInfo.cpp b/lib/Target/ARM/ARMBaseInstrInfo.cpp
index f5ae1b4..c92ec36 100644
--- a/lib/Target/ARM/ARMBaseInstrInfo.cpp
+++ b/lib/Target/ARM/ARMBaseInstrInfo.cpp
@@ -39,10 +39,6 @@
EnableARM3Addr("enable-arm-3-addr-conv", cl::Hidden,
cl::desc("Enable ARM 2-addr to 3-addr conv"));
-static cl::opt<bool>
-PredicateNEON("predicate-neon", cl::Hidden,
- cl::desc("Allow NEON instructions to be predicated"));
-
ARMBaseInstrInfo::ARMBaseInstrInfo(const ARMSubtarget& STI)
: TargetInstrInfoImpl(ARMInsts, array_lengthof(ARMInsts)),
Subtarget(STI) {
@@ -417,7 +413,7 @@
if ((TID.TSFlags & ARMII::DomainMask) == ARMII::DomainNEON) {
ARMFunctionInfo *AFI =
MI->getParent()->getParent()->getInfo<ARMFunctionInfo>();
- return PredicateNEON && AFI->isThumb2Function();
+ return AFI->isThumb2Function();
}
return true;
}
diff --git a/test/CodeGen/Thumb2/ifcvt-neon.ll b/test/CodeGen/Thumb2/ifcvt-neon.ll
new file mode 100644
index 0000000..c667909
--- /dev/null
+++ b/test/CodeGen/Thumb2/ifcvt-neon.ll
@@ -0,0 +1,29 @@
+; RUN: llc < %s -march=thumb -mcpu=cortex-a8 | FileCheck %s
+; rdar://7368193
+
+@a = common global float 0.000000e+00 ; <float*> [#uses=2]
+@b = common global float 0.000000e+00 ; <float*> [#uses=1]
+
+define arm_apcscc float @t(i32 %c) nounwind {
+entry:
+ %0 = icmp sgt i32 %c, 1 ; <i1> [#uses=1]
+ %1 = load float* @a, align 4 ; <float> [#uses=2]
+ %2 = load float* @b, align 4 ; <float> [#uses=2]
+ br i1 %0, label %bb, label %bb1
+
+bb: ; preds = %entry
+; CHECK: ite lt
+; CHECK: vsublt.f32
+; CHECK-NEXT: vaddge.f32
+ %3 = fadd float %1, %2 ; <float> [#uses=1]
+ br label %bb2
+
+bb1: ; preds = %entry
+ %4 = fsub float %1, %2 ; <float> [#uses=1]
+ br label %bb2
+
+bb2: ; preds = %bb1, %bb
+ %storemerge = phi float [ %4, %bb1 ], [ %3, %bb ] ; <float> [#uses=2]
+ store float %storemerge, float* @a
+ ret float %storemerge
+}