Encode the 32-bit wide Thumb (and Thumb2) instructions with the high order
halfword being emitted to the stream first. rdar://8728174
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120848 91177308-0d34-0410-b5e6-96231b3b80d8
diff --git a/lib/Target/ARM/ARMMCCodeEmitter.cpp b/lib/Target/ARM/ARMMCCodeEmitter.cpp
index d6926d9..bdac5ad 100644
--- a/lib/Target/ARM/ARMMCCodeEmitter.cpp
+++ b/lib/Target/ARM/ARMMCCodeEmitter.cpp
@@ -995,6 +995,7 @@
void ARMMCCodeEmitter::
EncodeInstruction(const MCInst &MI, raw_ostream &OS,
SmallVectorImpl<MCFixup> &Fixups) const {
+ const ARMSubtarget &Subtarget = TM.getSubtarget<ARMSubtarget>();
// Pseudo instructions don't get encoded.
const TargetInstrDesc &Desc = TII.get(MI.getOpcode());
uint64_t TSFlags = Desc.TSFlags;
@@ -1007,7 +1008,14 @@
case ARMII::Size2Bytes: Size = 2; break;
case ARMII::Size4Bytes: Size = 4; break;
}
- EmitConstant(getBinaryCodeForInstr(MI, Fixups), Size, OS);
+ uint32_t Binary = getBinaryCodeForInstr(MI, Fixups);
+ // Thumb 32-bit wide instructions need to be have the high order halfword
+ // emitted first.
+ if (Subtarget.isThumb() && Size == 4) {
+ EmitConstant(Binary >> 16, 2, OS);
+ EmitConstant(Binary & 0xffff, 2, OS);
+ } else
+ EmitConstant(Binary, Size, OS);
++MCNumEmitted; // Keep track of the # of mi's emitted.
}