commit d94b6a16fec7d5021e3922b0e34f9ddb268d54b1
author Owen Anderson <resistor@mac.com> Fri Jan 04 23:57:37 2008 +0000
committer Owen Anderson <resistor@mac.com> Fri Jan 04 23:57:37 2008 +0000
tree 93bca8eb4012a736aa39f6013957e95aac2cd792
parent 67d65bb69d5cad957cbb6d672dc0b4a19c211a42

Move some more functionality from MRegisterInfo to TargetInstrInfo.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45603 91177308-0d34-0410-b5e6-96231b3b80d8

lib/Target/X86/X86InstrInfo.h

diff --git a/lib/Target/X86/X86InstrInfo.h b/lib/Target/X86/X86InstrInfo.h
index 280d040..d39b865 100644
--- a/lib/Target/X86/X86InstrInfo.h
+++ b/lib/Target/X86/X86InstrInfo.h
@@ -296,6 +296,15 @@
                                SmallVectorImpl<MachineOperand> &Addr,
                                const TargetRegisterClass *RC,
                                SmallVectorImpl<MachineInstr*> &NewMIs) const;
+  
+  virtual bool spillCalleeSavedRegisters(MachineBasicBlock &MBB,
+                                         MachineBasicBlock::iterator MI,
+                                 const std::vector<CalleeSavedInfo> &CSI) const;
+
+  virtual bool restoreCalleeSavedRegisters(MachineBasicBlock &MBB,
+                                           MachineBasicBlock::iterator MI,
+                                 const std::vector<CalleeSavedInfo> &CSI) const;
+  
   virtual bool BlockHasNoFallThrough(MachineBasicBlock &MBB) const;
   virtual bool ReverseBranchCondition(std::vector<MachineOperand> &Cond) const;