Binary encoding for ARM tLDRspi and tSTRspi.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121186 91177308-0d34-0410-b5e6-96231b3b80d8
diff --git a/lib/Target/ARM/ARMMCCodeEmitter.cpp b/lib/Target/ARM/ARMMCCodeEmitter.cpp
index b011347..0376a16 100644
--- a/lib/Target/ARM/ARMMCCodeEmitter.cpp
+++ b/lib/Target/ARM/ARMMCCodeEmitter.cpp
@@ -156,6 +156,11 @@
uint32_t getAddrMode3OpValue(const MCInst &MI, unsigned OpIdx,
SmallVectorImpl<MCFixup> &Fixups) const;
+ /// getAddrModeThumbSPOpValue - Return encoding info for 'reg +/- imm12'
+ /// operand.
+ uint32_t getAddrModeThumbSPOpValue(const MCInst &MI, unsigned OpIdx,
+ SmallVectorImpl<MCFixup> &Fixups) const;
+
/// getAddrModeS4OpValue - Return encoding for t_addrmode_s4 operands.
uint32_t getAddrModeS4OpValue(const MCInst &MI, unsigned OpIdx,
SmallVectorImpl<MCFixup> &Fixups) const;
@@ -656,6 +661,20 @@
return (Rn << 9) | Imm8 | (isAdd << 8) | (isImm << 13);
}
+/// getAddrModeThumbSPOpValue- Encode the t_addrmode_sp operands.
+uint32_t ARMMCCodeEmitter::
+getAddrModeThumbSPOpValue(const MCInst &MI, unsigned OpIdx,
+ SmallVectorImpl<MCFixup> &Fixups) const {
+ // [SP, #imm]
+ // {7-0} = imm8
+ const MCOperand &MO = MI.getOperand(OpIdx);
+ const MCOperand &MO1 = MI.getOperand(OpIdx + 1);
+ assert (MO.getReg() == ARM::SP && "Unexpected base register!");
+ // The immediate is already shifted for the implicit zeroes, so no change
+ // here.
+ return MO1.getImm() & 0xff;
+}
+
/// getAddrModeSOpValue - Encode the t_addrmode_s# operands.
static unsigned getAddrModeSOpValue(const MCInst &MI, unsigned OpIdx,
unsigned Scale) {